Showing papers on "Design for testing published in 1991"

Design for testability using scanpath techniques for path-delay test and measurement

Abstract: 1. Abstract This paper describes a novel flip-flop design which is used in performing internal path-delay test and measurement using scanpath technique:;. Also described is the design for a boundary-scan cell that enables inpUtlOUtpUt delays to be measured. The paper includes a real-life application example.

Testing and Diagnosis of Analog Circuits and Systems

Abstract: 1. A Circuit Theoretic Approach to Analog Fault Diagnosis.- Background.- An Introduction to Analog Fault Diagnosis.- Important Issues of Analog Fault Diagnosis.- The Element-Value Solvability Problem.- A Fault/Tolerance Compensation Model.- k-Fault Diagnosis: The Ideal Case.- k-Fault Diagnosis: The Tolerance Case.- Illustrative Examples.- 2. Linear Method vs. Nonlinear Method.- Setting of the Problem.- Probability.- Probability Measure.- Perturbation of Parameters.- Geometry of SF and TF.- Linear Method Is as Powerful as the Nonlinear Method.- 3. Topological Testability Conditions for Analog Fault Diagnosis.- Theory.- Applications.- 4. Fault Diagnosis of Nonlinear Electronic Circuits.- Fault Diagnosis of Linear Circuits.- Fault Diagnosis of PWL Circuits.- Examples.- 5. Analog Multifrequency Fault Diagnosis with the Assumption of Limited Failures.- The CCM and the Fault Diagnosis Equations of [4].- A Motivational Example.- Diagnosability for nf Faults.- Limited Fault Algorithm.- Limited Fault Algorithm Examples.- 6. A Searching Approach Self-Testing Algorithm for Analog Fault Diagnosis.- Automatic Test Program Generation.- Decision Algorithms.- The Heuristic Algorithm.- Parallel Processing for Analog Fault Diagnosis.- Design for Testability.- 7. An Artificial Intelligence Approach to Analog Systems Diagnosis.- Qualitative Causal Models.- The Treatment of Fault Probabilities.- Best Test Strategies.- FIS: An Implemented Diagnostic System.- Current Applications of FIS.- 8. Automatic Testing for Control Systems Conformance.- Historical Development of ATE.- Transfer Function Testing.- Return Signal Processing.- Tuning of Large Electro-Mechanical Servosystems.- The SUT Test Signature.- Transfer Function Models of Control Systems.- The "Fuzzy" Nature of Control System Behavior.- Checkout Based on Quadratic Performance Criteria.- "Closed Loop" Testing.- 9. Testing of Analog Integrated Circuits.- Testing vs. Diagnosis.- Digital vs. Analog Testing.- Specification-Based Testing.- Solution of the Test Tolerance Assignment Problem.- Consideration for Fault-Model-Based Testing.- An Approach to Fault-Model-Based Testing.- 10. A Unified Theory on Test Generation for Analog/Digital Systems.- Notation and Basic Concepts.- Testability of Interconnected Systems.- Reachability, Observability, and Testability.- Test Generation for Interconnected Systems: Case Studies.

A data path synthesis method for self-testable designs

Abstract: A high level synthesis for testability method is presented whose objective is to generate self-testable RTL designs from data flow behavioral descriptions. The approach is formulated as an allocation problem based on an underlying structural testability model and its connection rules. Two allocation techniques have been developed to solve this problem: one based on an efficient heuristic algorithm that generates cost-effective designs, the other based on an integer linear program formulation that generates optimal designs. The allocation algorithms have been implemented and several benchmark examples are presented.

A design for testability scheme with applications to data path synthesis

Abstract: The recent progress of high level synthesis has illuminated an effective aid for system designers. To keep pace with the development of such an environment, there is a need to consider design for testability (DFT) during the synthesis process. This paper proposes a DFT scheme that can be coordinated with data path synthesis by an interactive trade-off process. The basis of this work is a system level testability model. To quantify the qualitative description of testability, a con- trollability measure and an observability measure is devel- oped. Based on these two measures, a procedure of trading- off between testing time and test hardware overhead is demonstrated. Featuring the ability to work on partial designs, this testing cost evaluation scheme is well suited to the demands of high level synthesis. Currently, simu- lation tools for obtaining testability measures have been completed and experiments have been conducted to vali- date this model.

The Art of Programming Embedded Systems

Abstract: Introduction. Initial Considerations. Elegant Structures. Design for Debugging. Design for Test. Memory Management. Approximations. Interrupt Management. Real-Time Operating Systems. Signal Sampling and Smoothing. A Final Perspective. Appendixes: Magazines. File Format. Serial Communications. Bibliography. Index.

Automated module testing in Prolog

Abstract: Tools and techniques for writing scripts in Prolog that automatically test modules implemented in C are presented. Both the input generation and the test oracle problems are addressed, focusing on a balance between the adequacy of the test inputs and the cost of developing the output oracle. The authors investigate automated input generation according to functional testing, random testing, and a novel approach based on trace invariants. For each input generation scheme, a mechanism for generating the expected outputs has been developed. The methods are described and illustrated in detail. Script development and maintenance costs appear to be reasonable, and run-time performance appears to be acceptable. >

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Abstract: In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.

Optimal VLSI Architectural Synthesis: Area, Performance and Testability

Abstract: I: Introduction.- 1. Global VLSI Design Cycle.- 1.1 VLSI Design Cycle.- 1.2 Hybrid Systems Design.- 1.3 Impact Of Technologies.- 1.4 Test Considerations.- 1.5 Bottlenecks and Open Issues.- 1.6 focus of Text.- 2. Behavioral and Structural Interfaces.- 2.1 Input to an Architectural Synthesizer.- 2.2 Interface Primitives for External Processes.- 2.3 Output Primitives from an Architectural Synthesizer.- II: Review And Background.- 3. State of the Art Synthesis.- 3.1 Terminology and Subtask Definitions.- 3.2 High Level Transformations.- 3.3 Independent Subtask Optimization.- 3.3.1 Scheduling.- 3.3.2 Resource Allocation.- 3.4 Iterative and Simultaneous Approaches.- 3.5 Mathematical Approaches.- 3.5.1 Branch and Bound.- 3.5.2 Simulated Annealing.- 3.5.3 Makespan Scheduling.- 3.5.4 Feasibility Models.- 3.6 Timing Constrained Synthesis.- 3.7 Cost Functions for Design Evaluation.- 4. Introduction to Integer Programming.- 4.1 Applications and Models.- 4.2 Solution of Unstructured IPs.- 4.3 Polyhedral Approaches To Solving Ips.- 4.4 The Node Packing Problem.- 4.5 The Knapsack Problem.- III: Optimal Architectural Synthesis With Interfaces.- 5. A Methodology for Architectural Synthesis.- 5.1 Requirements for High Level Synthesis Tools.- 5.2 High Level Methodology.- 5.3 OASIC Methodology.- 5.4 An Introduction to OASIC.- 5.5 Oasic Terminology, Assumptions, and Preprocessing.- 5.5.1 terminology.- 5.5.2 Assumptions.- 5.5.3 Preprocessing.- 6. Simultaneous Scheduling, and Selection and Allocation Of Functional Units.- 6.1 The Formal Model.- 6.2 Cost Functions.- 6.3 Functional Unit Type Selection.- 7. Oasic: Area-Delay Constrained Architectural Synthesis.- 7.1 The Precedence Constrained Scheduling Model.- 7.2 Functional Unit Allocation.- 7.3 Register Allocation.- 7.4 Bus Allocation.- 7.5 Cost Functions.- 7.6 Application Specific Tightening of Con-straints.- 8. Support for Algorithmic Constructs.- 8.1 Conditional Code.- 8.2 Loops.- 8.3 Functional Pipelining.- 9. Interface Constraints.- 9.1 General Interface: Minimum and Max-imum Timing Constraints.- 9.2 Analog Interface: Fixed Timing Con-straint.- 9.3 Asynchronous Interface.- 9.4 Unknown Unbounded Delays.- 9.5 Complex Timing Constraints.- 10. Oasic Synthesis Results.- 10.1 Elliptical Wave Filter.- 10.1.1 Structured Model.- 10.1.2 Area-delay Optimized.- 10.2 Neural Network Algorithm.- 10.3 Conditional Code Example.- 10.4 Analog and Asynchronous interface Examples.- 10.6.1 Analog Interface.- 10.6.2 Asynchronous Interface.- IV: Testable Architectural Synthesis.- 11. Testability in Architectural Synthesis.- 11.1 Design and Test.- 11.1.1 Choices in Design and Test.- 11.2 Approaches to Testability.- 11.2.1 Test Measures and Tools.- 11.2.2 Design Modifications for Testability.- 11.3 Previous Research in Design for Test.- 11.4 Approaches To Test With Synthesis.- 11.4.1 Previous Research.- 11.4.2 Commercial Systems.- 11.5 Inadequacies of Current Synthesis With Test.- 11.5.1 Feedback.- 11.5.2 Integration.- 11.5.3 Constraint Estimation.- 12. The Catree Architectural Synthesis With Testability.- 12.1 problem description.- 12.2 Comparison With Previous Research.- 12.3 Two Synthesis With Test Methodologies:Catree & Catree2.- 12.4 Catree Design Synthesis Stages.- 12.4.1 Input Specification.- 12.4.2 Design Allocation.- 12.4.3 Catree Area and Delay Estimates.- 12.4.4 Test Incorporation.- 12.4.5 Feedback.- 12.5 Catree Synthesis Results.- 12.6 Catree Discussion.- 12.7 Catree2 Design Synthesis stages.- 12.7.1 Tree Formation and Functional Unit Binding.- 12.7.2 Test Incorporation.- 12.7.3 (Test) Register and Bus Binding.- 12.7.4 Feedback.- 12.8 Catree2 Experiments.- 12.9 Catree2 Discussion.- V: Summary and Future Research.- 13. Summary and Future Research.- 13.1 Oasic Summary.- 13.2 Catree Summary.- 13.3 Future Extensions.- 13.4 Concluding Remarks.- References.

Ic defects-based testability analysis

Abstract: High quality IC design involves not only performance and silicon area, but also testability. Product quality, measured by low dejects levels (as low as 100 p.p.m.), requires that test patterns must detect nearly all circuit faults caused by likely physical defects. This requires a careful examination of the testability of the physical design, and its enhancement. The purpose of this contribution is to present a methodology for physical testability evaluation, and to demonstrate its usefulness. The methodology allows realistic fault extraction and classification, and the identification of hard to detect faults, their layout location and physical origin, prior to simulation. Measures of physical testability and fault hardness are introduced. When possible, suggestions for design improvement by layout reconfiguration, are provided, as a better solution than simple test improvement, either by test pattern refinement, or by using more sophisticated detection techniques, like current testing. Simulation results, with several design examples, show that layout styles exhibit characteristic pat.terns, in terms of t,he incidence of faults caused by the different, physical defects. Hence, for each layout style, the sensivity of physical designs to each physical defect can be analysed and decreased. Moreover, simulation results with a new cell library demonstrate that physical design improvements can significantly enhance the circuit’s qualit,y and testability.

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control

Abstract: In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in. >

Economic effects in design and test

Abstract: The authors argue that because of misconceptions and myths about the cost of test, many devices and systems are inadequately tested. Focusing on application-specific integrated circuits (ASICs), the authors discuss the economics of test and show how economic analysis leads to test that pays back. The EVEREST test strategy planner, a design tool that aids in the selection of design-for-testability structures during ASIC design and uses cost as a primary selection parameter, is presented. >

A design-for-testability architecture for multichip modules

Abstract: Board real estate requirements and execution speed demands['] ,are contributing to the compressing of logic circuits to the point where test accessibility is becoming more and more difficult. The extreme of this trend is the multichip module, where accessibility at other than the 1/0 pins is inon-existent. Therefore, the testing of these devices is proving to be a difficult and tedlous problem which must be solved before commercial production of these devices can become commonplace. Through the use of a design-for-testability architecture involving boundary-scan coupled with other board-test techniques, this process can be made more manageable.

A framework for design for testability of mixed analog/digital circuits

Abstract: Three analog design-for-testability (DFT) schemes used to test the analog portion of a mixed-signal circuit are presented. The mixed-signal device-under-test is partitioned into analog and digital macros and structured access is provided to the analog macros to enhance observability and controllability. The proposed test methodology integrates analog testing with the existing digital test techniques to form a single DFT framework for mixed-signal devices. >

A methodology for testability enhancement at layout level

Abstract: In order to make possible the production of cost-effective electronic systems, integrated circuits (ICs) need to be designed for testability. The purpose of this article is to present a methodology for testability enhancement at the lower levels of the design (i.e., at circuit and layout levels). The proposed strategy uses both hardware refinement and software improvement. The main areas of low-cost software improvement are test generation based on a logic description closely related to the physical design, test-vector sequencing, and the introduction of circuit knowledge in fault simulation. The strategy for hardware improvement is based on realistic fault list generation, fault classification (according to fault impact on circuit behavior), and layout-level DFT (design for testability) rules derivation. A preliminary fault classification is proposed, which uncovers the types of realistic faults in MOS digital ICs that are hard to detect, paving the way to derive layout rules for hard-fault avoidance. Simulation examples are presented ascertaining that specific subsets of line-open and bridging faults (according to their topological characteristics) are hard to detect by logic testing using test patterns derived for line stuck-at fault detection.

Design of CMOS circuits for stuck-open fault testability

Abstract: A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes. >

Test Propagation Through Modules and Circuits

Abstract: Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.

Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II

Abstract: The SFG-tracing methodology addresses the automatic verification of digital synchronous circuit implementations as specified at the algorithmic level as signal- (SFG) or data flow graphs. The SFG-tracing methodology is a multi-level design verification paradigm that aims at bridging the gap between higher level specifications down to lower level implementations up to the transistor switch level. The concepts of the SFG-tracing methodology are illustrated by the automatic verification of a transistor level implementation of a small chip generated from its high level specification by the Cathedral-II silicon compiler. This application, although simple, includes a datapath, register files, a multi-branch micro coded controller, and additional circuitry as necessary for design for testability measures. This application illustrates the SFG-tracing verification methodology as applied to one member of a partitioned SFG behavioral specification. Experimental results on more complex, completely verified designs of 32000 transistors demonstrate the feasibility of the approach. >

Achieving complete delay fault testability by extra inputs

Abstract: The problem of designing complete path delay fault testable combinational circuits is considered. To supplement existing synthesis and design for testability procedures, we propose a method for augmenting a given two-level circuit by adding extra inputs, such that the resulting circuit is fully robust hazard-free testable for path delay faults. The following results are shown. For the case where a single input is sufficient to make a circuit fully testable, we provide a simple method for adding that input, which always guarantees full testability. When a single input is not sufficient to make the circuit fully testable, we provide a method for computing a lower bound on the number of inputs required. The two resullts are then combined and augmented by other rules, to yield a method for obtaining fully testable circuits. Experimental results are given, to show that full testability can practically be achieved by adding a small number of inputs.

Testability features of the 68hc16z1

Abstract: The purpose of this paper is to describe the testability features implemented in Motorola's recently completed design of a sixteen bit microcontroller, the 68HC16Z1. The discussion includes a brief introduction to the 68HC16Z1, test objectives and organization along with descriptions of design for test (DR) techniques and structures.

Design verification using logic tests

Abstract: Design verification is the process of assuring that a design is error-free. Empirical design verification involves the running of test cases against the design. To be effective, 'sufficient' testing must be performed. But to be cost-effective as well, testing must be terminated when that point is reached. There is a lack of quantifiable metrics to guide the development of tests for digital logic design verification. The authors report on the results of experiments that indicate that fault simulation, which parallels the well-known mutation testing approach used in software design verification, can be used to grade the coverage of test cases used for hardware design verification. >

A new low overhead design for testability of programmable logic arrays

Abstract: A new design to reduce the overhead required for fully testable programmable logic arrays (PLAs) is proposed. This design exploits the fact that product lines in a PLA can be rearranged and grouped into few partitions. Then, some extra outputs are added, one per partition, to make the whole PLA testable. Compared with the previous PLA design-for-testability techniques, the algorithm presented is very feasible, and its implementation is straightforward. Furthermore, this algorithm significantly lowers overhead and provides substantially higher fault coverage than some existing schemes. >

Digital Circuit Testing: A Guide to DFT and Other Techniques

Abstract: A Test Generation Method Using Testability Results. Circuit ATVG and DFT. PLD Design for Test. Built-In Self Test and Boundary Scan Techniques. ATE and the Testing Process. Special Testing Topics and Conclusions. Index.

VLSI circuits and systems in silicon

Abstract: Mos models mipolar models Cmos digital models Cmos analogue circuits bipolar digital circuits bipolar analogue circuits mapping algorithm to silicon - some examples digital systems floor planning and chip architecture alternative design styles principles of testing design for testability Mos processes bipolar processes design rules verification and scaling high level simulation logic simulation circuit simulation placement and rounting.

Implementing 1149.1 on cmos microprocessors

Abstract: Selected implementation issues of IEEE 1149.1 Std. Test Access Port and Boundary-Scan Architecture are described for three Motorola VLSI CMOS microprocessors. F’roblems and solutions that arose during implementation of standard features and additional public instructions are discussed.

Designing self-testable cellular arrays

Abstract: Design-for-testability techniques and built-in self-test structures are presented for cellular arrays based on the M-testability condition, which results in the minimal number of tests. This technique applies to arrays with arbitrary dimensions and various connections. A systolic array multiplier is given as an example, showing an overhead of only 4% for making it M-testable. This method compares favorably with that based on pI-testability. It reduces drastically the testing costs for circuits realized as cellular arrays. >

BIDES: a BIST design expert system

Abstract: BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.

A testable model for stoppable clock ASICS

Abstract: A testable model for globally asynchronous ASICs is presented. These circuits operate without a global clock and are useful for pipelined or data-driven architectures. The ASIC can be partitioned into several locally clocked modules and control is distributed throughout these modules. A test methodology is presented which partitions each locally clocked module into synchronous and asynchronous components in test mode. Design for testability techniques are used to further simplify the testing process. >

Bipolar, CMOS and BiCMOS circuit technologies examined for testability

Abstract: A circuit-level testability comparison of bipolar, CMOS and BiCMOS logic technologies is presented. Process defects from each technology are examined to determine the fault models that best detect these defects. Commonalities and differences of fault models among the circuit types are described. The test cost required to obtain the same quality in each technology is described. It is shown that bipolar circuits can be effectively tested by the stuck fault model. To achieve high test coverage in CMOS circuits, stuck fault and current testing should be applied. Current testing can be effective in CMOS if the appropriate patterns are generated. BiCMOS requires delay testing. While current measurement could detect a few defects, it is not enough to replace delay test in BiCMOS. Delay testing may not detect all defects even if test vectors are available. Furthermore, it is expensive in test generation and test hardware cost. This suggests that design-for-test features may even be more important for BiCMOS circuits than for CMOS or bipolar circuits. >

Partitioning hierarchical designs for testability

Abstract: This paper describes the partitioning subsystem of MCC's Testability Insertion Guidance ExpeRt system (TIGER) [2]. TIGER addresses Design for Testability issues by employing a divide and conquer strategy which permits auser to analyze testability problems early in a design cycle, and make intelligent decisions about the applicability of various test methods to circuit partitions. This paper describes the methodology used in Tiger to partition hierarchical designs for test purposes.