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Showing papers on "Design for testing published in 1994"


Journal ArticleDOI
TL;DR: This article maps the testability terrain for object-oriented development to assist the reader in finding relatively shorter and cheaper paths to high reliability.
Abstract: estability is the relative ease and expense of revealing software faults. This article maps the testability terrain for object-oriented development to assist the reader in finding relatively shorter and cheaper paths to high reliability. Software testing adds value by revealing faults. It is fundamentally an economic problem characterized by a continuum between two goals. A reliability -dtiven process uses testing to produce evidence that a pre-release reliability goal has been met. Time and money are expended on testing until the reliability goal is attained. This view of testing is typically associated with stringent, quantifiable reliability requirements. Other things being equal, a more testable system will reduce the time and cost needed to meet reliability goals. A resource-limited process views testing as a way to remove as many rough edges from a system as time or money permits. Testing continues until available test resources have been expended. Measurement of test adequacy or system reliability are incidental to the decision to release the system. This is the typical view of testing. Other things being equal, a more testable system provides increased reliability for a fixed testing budget.

305 citations


Proceedings ArticleDOI
02 Oct 1994
TL;DR: A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds.
Abstract: A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits.

158 citations


Proceedings ArticleDOI
28 Feb 1994
TL;DR: Genesis provided 100% system-level testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator.
Abstract: Previous research in the area of behavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault effects from module outputs to system outputs Genesis provided 100% system-level testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator The area overhead of circuits synthesized by Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability Genesis can also easily handle loop constructs in the behavioral specification >

74 citations


Journal ArticleDOI
Y. Zorian1
TL;DR: In this paper, a structured testability approach for multi-chip module (MCM) is presented, which is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is independent of silicon, substrate or attachment technologies.
Abstract: Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution. >

70 citations


Journal ArticleDOI
TL;DR: Test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points, which has the major advantage of using TSI is a low pin count and test application time as compared to testPoint insertion andpartial scan.
Abstract: In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit's behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented. >

64 citations


Proceedings ArticleDOI
06 Nov 1994
TL;DR: A new testability measure is developed, and the RT-level structure of the data path is utilized for cost-effective re-design of the circuit to make it easily testable, without having to either scan any flip-flop or breakloops directly.
Abstract: This paper presents a non-scan design-for-testability technique applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new testability measure, and utilize the RT-level structure of the data path, for cost-effective re-design of the circuit to make it easily testable, without having to either scan any flip-flop or breakloops directly. The non-scan DFT technique was applied to several data path circuits. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed. The hardware overhead and the test application time required for the non-scan designs is significantly lower than the corresponding partial scan designs.

62 citations


Proceedings ArticleDOI
06 Jun 1994
TL;DR: Experimental results show that designs generated by this approach are testable in a highly concurrent manner.
Abstract: The testability of a VLSI design is strongly affected by its register-transfer level (RTL) structure. Since the high-level synthesis process determines the RTL structure, it is necessary to consider testability during high-level synthesis. A synthesis system composed of scheduling and binding components minimizes the number of hardware sharing conicts between tests in the test schedule. Novel test conict estimates are used to direct the synthesis process. The test conflict estimation is based on examination of the interconnect structure of the partial design state during synthesis. Test conict estimates enable our synthesis system to select design options which increase test concurrency, thereby decreasing test time. Experimental results show that designs generated by this approach are testable in a highly concurrent manner.

52 citations


Journal ArticleDOI
TL;DR: The structure and operation of the main types of semiconductor memory are described, and the different contexts in which memories are tested together with the corresponding different types of tests are described.
Abstract: This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.

52 citations


Proceedings ArticleDOI
25 Apr 1994
TL;DR: A design-for-test technique for switched-capacitor filters to improve controllability and observability of internal nodes and timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability.
Abstract: The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability. The overhead in terms of extra control logic is small (several simple gates). Since there are no extraneous devices inserted in the analog signal path, there is no performance penalty in the normal operation of the filters. >

50 citations


Proceedings ArticleDOI
25 Apr 1994
TL;DR: A new strategy for testing analog filters is presented, based on the reevaluation of the transfer function followed by simple processing of the output signals, which consists in provoking pole-zero cancellation during the test mode, without eliminating information about parameters which determine the normal circuit operation.
Abstract: A new strategy for testing analog filters is presented, based on the reevaluation of the transfer function followed by simple processing of the output signals. Taking advantage of the structural properties of some universal biquads, this new strategy consists in provoking pole-zero cancellation during the test mode, without eliminating information about parameters which determine the normal circuit operation. Although area overhead could seem high, it can be very small in many applications. >

45 citations


Proceedings ArticleDOI
29 Jun 1994
TL;DR: TEAMS consists of algorithms based on information theory, heuristic search, and graph theory to optimize design, diagnosis and maintenance of integrated systems and thereby reduce the life-cycle cost.
Abstract: TEAMS, Testability Engineering and Maintenance System, is a software package for testability analysis, automatic test sequencing, and design for testability of complex, hierarchically-described, modular systems. It consists of algorithms based on information theory, heuristic search, and graph theory to optimize design, diagnosis and maintenance of integrated systems and thereby reduce the life-cycle cost. A system is modeled as a hierarchical directed dependency graph with special nodes to denote modules, test points, modes of operation and redundancy. Links in the graph denote first order functional dependencies. TEAMS supports hierarchical testing in accordance with the field maintenance procedures; a failure source may be isolated to a component or a module at any level. Other practical features include options to integrate diagnosis with rectification, and to optimize diagnostic time and/or cost. An interactive menu-mouse graphical interface serves as a high-level front-end to these algorithms and enables the user to graphically enter, modify and integrate hierarchical functional models of systems. TEAMS presents concise testability reports consisting of important detection and isolation figures of merit, testability shortcomings and design for testability recommendations.

Proceedings ArticleDOI
25 Apr 1994
TL;DR: A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan registers to break all cycles as compared to the original circuit.
Abstract: This paper presents a technique to enhance the testability of sequential circuits by repositioning registers. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan registers to break all cycles (except self-loops) as compared to the original circuit. The retiming technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit to minimize the number of registers in the SCCs. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique. >

Proceedings ArticleDOI
02 Oct 1994
TL;DR: The key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug are described.
Abstract: MicroSPARC is a highly integrated, high volume, low-cost CMOS RISC microprocessor. To meet the design goals, it included fully synchronous logic with full testability support, using scannable flops and a JTAG-compliant clock controller. This paper describes the key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug. The paper concludes with a discussion of lessons learned. A related paper (1994) describes the methodologies used and benefits realized in the tester environment, along with data collected during the debug phase of the project.

Proceedings ArticleDOI
10 Oct 1994
TL;DR: The methods presented can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining.
Abstract: Most existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits (S. Bhatia and N.K. Jha, 1994). In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads. >

Proceedings ArticleDOI
06 Jun 1994
TL;DR: Test-point insertion is done to reduce the number of paths, using a time-efficient procedure, and also reducesThe number of tests and renders untestable paths testable.
Abstract: We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Proceedings ArticleDOI
02 Oct 1994
TL;DR: The testability strategy and design-for-test features of the Alpha AXP 21164 microprocessor are described and the innovative solutions employed to solve them are discussed.
Abstract: This paper describes the testability strategy and design-for-test features of the Alpha AXP 21164 microprocessor. It discusses the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them.

Proceedings ArticleDOI
Kenneth L. McMillan1
06 Jun 1994
TL;DR: This tutorial introduces several methods of formal hardware verification that could potentially have a practical impact on the design process, and considers where the various methods might fit into the life cycle of a design, what their capabilities and shortcomings are, and how thedesign process might change in order to accommodate formal methods.
Abstract: This tutorial introduces several methods of formal hardware verification that could potentially have a practical impact on the design process. The measure of success in integrating these methods into a design methodology is arguably not the ability to provide formal guarantees of correctness, but rather to detect design errors in a timely manner, as the design evolves. Based on this criterion, and some limited practical experience, we consider where the various methods might fit into the life cycle of a design, what their capabilities and shortcomings are, and how the design process might change in order to accommodate formal methods.

Proceedings ArticleDOI
02 Oct 1994
TL;DR: The design choices that were made and the considerations that led to those choices are explored, and the architectures and methodologies used to implement the design choices are presented.
Abstract: This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test methodologies and architectures.

Proceedings ArticleDOI
10 May 1994
TL;DR: The aim of this work is to present a new symbolic approach for testability measurement of analog networks based only on the study of the network function symbolic coefficients, which presents noteworthy advantages from a computational point of view with respect to previous techniques.
Abstract: Testing an electronic circuit is a vital part of its overall design and fabrication process. This problem is even going to be more critical with technology improvements and with the coexistence on a chip of analog and digital components. In fact the testing of mixed signal microsystems is very difficult compared to digital only devices. They do not lend themselves to earlier and simpler test routines. The entire mixed signal segment is hampered by the lack of design for testability methodologies and tools. In this field the concept of analog circuit testability is of fundamental importance. The aim of this work is to present a new symbolic approach for testability measurement of analog networks. The new method presents noteworthy advantages from a computational point of view with respect to previous techniques. In fact it does not require the computation of the sensitivities of the network functions but it is based only on the study of the network function symbolic coefficients. The new approach allows also the formulation of simple necessary conditions for maximum testability based only on the order of the network functions. >

Journal ArticleDOI
TL;DR: It is demonstrated that a DFT tool can make a more efficient and effective selection of partial scan flip-flops by exploiting the high-level circuit information and can accurately predict the hard-to-test areas of a circuit.
Abstract: The increasing use of hardware description languages (HDL's) in VLSI design and the emergence of high-level test generation programs has led to an interesting problem. There is a need for design for testability (DFT) techniques that can be applied early in the design phase to improve the effectiveness of ATPG programs on hard-to-test circuits. By an early identification of hard-to-test areas of a circuit, testability can be inserted prior to logic synthesis. In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on an evaluation of the results, we propose techniques to automatically extract information from the high-level circuit description that could improve the performance of both ATPG tools. An automatic DFT tool that utilizes VHDL descriptions of the circuit to make an intelligent selection of flip-flops for partial scan is then described. Results on six hard-to-test circuits show that very high fault coverages can be obtained by both a gate-level and a high-level test generator on these circuits after scan. With this detailed study we demonstrate that a DFT tool can make a more efficient and effective selection of partial scan flip-flops by exploiting the high-level circuit information. It can accurately predict the hard-to-test areas of a circuit. Significant improvements in fault coverage and ATPG efficiency, and speedups in ATPG time, can be obtained by a gate-level and a high-level test generator after high-level scan selection. >

Proceedings ArticleDOI
C. Hunter1, E.K. Vida-Torku2, J. LeBlanc2
02 Oct 1994
TL;DR: The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.
Abstract: The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.

Proceedings ArticleDOI
02 Oct 1994
TL;DR: A new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead is presented.
Abstract: In this paper we present a new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead. The technique uses selective bit-fixing plus biased pseudorandom patterns and is referred to as fixed-biased pseudorandom BIST. An automatic design tool (FBIST) specifies the necessary information for implementation of the BIST hardware. The amount of hardware overhead introduced is controlled by user specified parameters and can therefore meet varying design specifications. Since the proposed technique relies on bit-fixing, we present a new scan cell which supports bit-fixing. Results are presented for combinational benchmark circuits and comparisons made with prior techniques with respect to test application time and hardware overhead.

Proceedings ArticleDOI
10 Oct 1994
TL;DR: A system which synthesizes, from a behavioral description, an RTL circuit which is testable with a high degree of test concurrency, and produces a datapath containing test registers and a BIST test plan for the testing of the chip.
Abstract: We present a system which synthesizes, from a behavioral description, an RTL circuit which is testable with a high degree of test concurrency. The system produces a datapath containing test registers, and a BIST test plan for the testing of the chip. All design decisions are made using an estimate of test conflicts, which is based on an analysis of the reachability of each component port from I/O pins and test registers. Chip testing according to the partial-intrusion BIST methodology is assumed. Empirical results show the effect of test conflicts on the test application time, and highlight the benefit of using the proposed synthesis approach for test conflict reduction. >

Journal ArticleDOI
TL;DR: This paper addresses pseudo-exhaustive test pattern generation requirements by inserting a small number of bypass storage cells in the circuit under test and constructing appropriate Linear Feedback Shift Registers to serve as built-in test pattern generators.
Abstract: In order for pseudo-exhaustive test pattern generation to be practical (time requirement less than 2/sup /spl omega//, /spl omega//spl les/20), two conditions must be satisfied: 1). The function of every element in the circuit must be controllable from no more than /spl omega/ inputs, and 2). The overall time to exercise all elements in the circuit must not exceed 2/sup /spl omega//. We address both these requirements by inserting a small number of bypass storage cells in the circuit under test and constructing appropriate Linear Feedback Shift Registers (LFSRs) to serve as built-in test pattern generators. Our method is applicable to both the gate-level and the module-level and achieves low hardware overhead by using a new graph model for the representation of the circuit and a metric quantity that couples requirements 1 and 2 above. >

Journal ArticleDOI
TL;DR: This analysis of the trade-offs associated with test strategies for complex multichip systems and modules clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable.
Abstract: Incorporating test and fault diagnosis as critical design requirements is necessary to achieve high-quality, cost-effective multichip systems. However, evaluating where and when to test, and deciding upon the best test method and level, take considerable study. The authors explore the trade-offs between various MCM test and rework strategies, then analyze the impact of cost, yield, and test effectiveness of the final cost and quality. This analysis of the trade-offs associated with test strategies for complex multichip systems and modules clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable. These methods result in cost reduction as well as quality improvement, and indicate that the MCM cost could vary by about 10% to 20%, depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, require an evaluation of the economics of the various solutions and the payback. This process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environments. >

Journal ArticleDOI
TL;DR: A design-for-test method that permits at-speed testing is introduced based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator.
Abstract: Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method that permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults that can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness was achieved on all but two circuits. >

Proceedings ArticleDOI
02 Oct 1994
TL;DR: This paper introduces two novel algorithms to test a very popular type of FIFO, namely the ring-address FifO, which provides full fault coverage for a comprehensive fault model.
Abstract: FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n/sup 2/) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described.

Proceedings ArticleDOI
05 Jan 1994
TL;DR: This paper describes the design of a self-checking operational amplifier and the associated subcircuits and develops and discusses methods to design members of this new class of analog circuits, self- checking analog circuits.
Abstract: In this paper we introduce a new class of analog circuits, self-checking analog circuits. We develop and discuss methods to design members of this new class. We target the class of fully differential analog circuits and use the inherent dual-rail code to develop self-checking circuits. We describe the design of a self-checking operational amplifier and the associated subcircuits. Our methodology has wide application as many analog circuits already are or can be transformed into fully differential circuits. >

Proceedings ArticleDOI
02 Oct 1994
TL;DR: A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed and simulation results are provided to show the accuracy of the metrology.
Abstract: A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology.

Proceedings ArticleDOI
02 Oct 1994
TL;DR: In this article, the authors present strategies for controlling on-chip design-for-test and built-in self-test (BIST) circuitry under a partially distributed test control architecture.
Abstract: We present strategies for controlling on-chip design-for-test (DFT) and built-in self-test (BIST) circuitry under a partially distributed test control architecture. These include mechanisms for broadcasting control information from apt integrated TAP controller over an infernal test bus, techniques for creating symbolic descriptions of local decoders that employ this information to control test resources, and algorithms for encoding the bus information. The encoding algorithms minimize a two-level implementation of the integrated TAP controller and/or the distributed decoders. These control strategies are IEEE 1149.1 boundary scan standard compliant and are applicable to both simple and complex DFT/BIST methodologies including those that employ multifunction and/or reconfigurable test registers and reconfigurable scan chains.