Showing papers on "Design for testing published in 1997"

Analog and mixed-signal benchmark circuits-first release

Abstract: The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

Test requirements for embedded core-based systems and IEEE P1500

Abstract: Chips comprising reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based system design. Using embedded cores enables the design of high-complexity system-chips with densities as high as millions of gates on a single die. The increase in using pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This paper discusses in general the challenges in testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and introduces the on-going standardization efforts, specifically under IEEE P1500 Working Group, which is meant to standardize the interface between a core test and its host the System-on-Chip.

Arithmetic Built-In Self-Test for Embedded Systems

Abstract: 1. Built-In Self-Test. Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST Schemes for Random Logic. BIST for Memory Arrays. 2. Generation of Test Vectors. Additive Generators of Exhaustive Patterns. Other Generation Schemes. Two-Dimensional Generators. 3. Test-Response Compaction. Binary Adders. 1's Complement Adders. Rotate-Carry Adders. Cascaded Compaction Scheme. 4. Fault Diagnosis. Analytical Model. Experimental Validation. The Quality of Diagnostic Resolution. Fault Diagnosis in Scan-Based Designs. 5. BIST of Data-Path Kernel. Testing of ALU. Testing of the MAC Unit. Testing of the Microcontroller. 6. Fault Grading. Fault Simulation Framework. Functional Fault Simulation. Experimental Results. 7. High-Level Synthesis. Implementation-Dependent Fault Grading. Synthesis Steps. Simulation Results. 8. ABIST at Work. Testing of Random Logic. Memory Testing. Digital Integrators. Leaking Integrators. 9. Epilog. Bibliography. A. Tables of Generators. B. Assembly Language. Index.

A low overhead design for testability and test generation technique for core-based systems

Abstract: In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level DFT to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level DFT and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used to tackle the above problem is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on two example systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Efficient and accurate testing of analog-to-digital converters using oscillation-test method

Abstract: This paper describes a practical test approach for analog-to-digital converters (ADCs) based on the oscillation-test strategy. The oscillation-test is applied to convert the ADC under test to an oscillator. The oscillation frequencies are able to monitor the ADC conversion rate, differential nonlinearity (DNL) and integral nonlinearity (INL) at each quantization band edge (QBE). Using this method, no analog stimulus should be supplied and therefore the need for a costly precision signal generator is eliminated. Besides, as the oscillation frequency is evaluated using pure digital circuitry, test accuracy is increased. This test approach is not limited to a special kind of ADC. Simulations and practical implementation prove the efficiency of the proposed test approach for ADCs.

Pentium(R) Pro processor design for test and debug

Abstract: This paper describes the Design for Test (DFT) and silicon debug features of the Pentium(R) Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Abstract: In recent years, there has been growing interest in behavioral (high-level) synthesis for testability. This is due to the fact that testability features, such as scan or the built-in self-test, may incur large overheads if introduced during logic synthesis in the later phase of the design cycle. Related previous work attempted to generate system-level test sets using hierarchical testability during behavioral synthesis. There, the test generation scheme is independent of bit width and is, therefore, capable of handling complex controller/data path circuits with large data path bit widths (e.g., 32), which has posed a serious challenge to logic-level sequential test generators. However, this previous work is not applicable when another high-level synthesis system is used. In this paper, we present techniques that add minimal test hardware to a given register-transfer level (RTL) circuit obtained by behavioral synthesis in order to ensure that the embedded elements in the circuit are hierarchically testable. An important byproduct of our design for testability (DFT) procedure is a system-level test set that delivers precomputed test sets to each element in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the combined controller/data path. We performed extensive experiments with several complex controller/data path circuits synthesized by three different high-level synthesis systems which do not target testability. The key advantages of our method, illustrated by these experiments, include: 1) the area, delay, and power overheads incurred for testability are very low (the average area, delay, and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4%, respectively), 2) both the DFT hardware addition and test generation algorithms are independent of the data path bit width.

Test ready compiler for design for test synthesis

Abstract: A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells. To account for chaining during compile, the TR compiler provides output driven loopback connections to simulate electrical characteristics of the chain during compile. In the above implementation, the TR compiler can efficiently provide translation of an HDL description with test implementations into a gate level netlist. With the addition of certain information regarding the test implementation (e.g., scan replacement is done and loopback connections are added), the TR compiler of the present invention can better optimize the overall layout for the addition of the test resources.

Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology

Abstract: This paper investigates parametric and catastrophic fault coverage of the oscillation-test strategy. A set of definitions to evaluate the efficiency of a test technique and to quantify the parametric fault coverage is therefore introduced. The oscillation-test strategy is a low-cost and practical test method which is very efficient for built-in self-testing of mixed-signal integrated circuits. Active analog filters are used as test vehicle and therefore design for testability techniques to convert them to oscillators have been presented. Discrete practical realizations and extensive simulations based on CMOS 1.2 /spl mu/m technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead.

Using BIST control for pattern generation

Abstract: A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.

Testability features of AMD-K6/sup TM/ microprocessor

Abstract: This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.

A Practical Method for Rigorously Controllable Hardware Design

Abstract: We describe a method for rigorously specifying and verifying the control of pipelined microprocessors which can be used by the hardware designer for a precise documentation and justification of the correctness of his design techniques. We proceed by successively refining a one-instruction-at-a-time-view of a RISC processor to a description of its pipelined implementation; the structure of the refinement hierarchy is determined by standard instruction pipelining principles (grouped following the kind of conflict they are designed to avoid: structural hazards, data hazards and control hazards).

Modifying user-defined logic for test access to embedded cores

Abstract: Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (UDL) surrounding the core may restrict the set of test vectors that can be applied to the core. Consequently, some of the core test vectors specified by the core supplier may not be contained in the output space of the UDL that drives the core and hence cannot be justified at the core inputs. Conventional solutions to this problem involve placing multiplexers or boundary scan elements at the inputs of the core to provide test access. This can be very costly in terms of area and performance. This paper presents a new approach for providing test access to an embedded core. A procedure is described for inserting control points in the UDL to modify its output space so that it contains the specified core test vectors. The flexibility in selecting the location of the control points is used to avoid performance degradation by keeping test logic off the critical timing paths. Experimental results are shown comparing the control point insertion procedure with other approaches.

Design for testability and built-in self-test of mixed-signal circuits: a tutorial

Abstract: The advent of new electronic packaging technologies has fueled the drive towards rapid integration of digital and analog functions particularly in portable computing and communications applications. This integration of digital and analog circuits into closely coupled mixed-signal circuits has brought with it, many challenges in the design and test areas. The problem in testing mixed-signal circuits arises from the simple fact that digital and analog fault models are inherently different. Moreover, while digital fault models are well understood (i.e. stuck-at faults), analog fault models are not quite as well-defined and mature. Another key problem stems from the fact that analog signals are inherently imprecise. Hence, with any analog measurement one must associate an accuracy of measurement. For large systems, it therefore becomes necessary to incorporate design for testability and built-in self-test (BIST) features in order to achieve high coverage of digital and analog faults. Also, with use of these features, fault simulation and test generation becomes easier. In the following paper, the authors discuss recent work in the area of design for testability and BIST.

Design of modular digital circuits for testability

Abstract: Modular products and reconfigurable testing processes are crucial in modern manufacturing. This paper discusses the concept of product modularity, test modules of increased reusability and exchangeability, and some aspects of design for testability. A methodology for design of modular products for testability in the presence of testing modules is developed. An integrated approach to design of modular products and test processes is discussed. The relationship between product modularity and design for testability is explored. This paper focuses on digital circuits which may be difficult to decompose into modules. The impact of testability on module sizes is considered. The testability points are identified at the circuit level while modular testing is considered at the board and system level. The main contribution of this paper is in the development of a formal approach to modularize products, and to assess the impact of modularity on the design process and testability.

Digital integrated circuit design system and methodology with hardware

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

On-line testable logic design for FPGA implementation

Abstract: In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system.

Intelligent reasoning assistant for incorporating manufacturability issues into the design process

Abstract: This paper describes an integrated Intelligent Reasoning Assistant (IRA) as an approach to incorporate manufacturability issues into the design process. By using a series of pre-established geometric features available from a CAD system and manufacturing knowledge captured from experienced design and manufacturing personnel, the proposed model is used to recommend feasible manufacturing process sequences and design changes that enhance design manufacturability early in the conceptual design stage. The used Design For Manufacturing (DFM) approach assumes that incorporating manufacturing issues into the design process is not a serial decision method, rather, it is a process with multiple parallel interactions from origination of a conceptual design to direct linkage with manufacturing parameters. Although the emphasis of this research has been focused on part designs which are metal machining intensive, it is believed that the described approach can be generalized to other manufacturing environments.

Design of oscillation-based test structures for active RC filters

Abstract: Summary form only given. We apply the oscillation-based test strategy to test active RC filters. We develop general guidelines for the design of the oscillation-based test structures and describe in more details the resonator active filler (biquad filter) configuration. It can be shown that some of the derived structures are achieved by simple circuit modification while for the more general case additional feedback loop network is required.

Microarchitectural synthesis for rapid BIST testing

Abstract: The impact of testability on design cost necessitates its consideration during the earliest stages of synthesis. Built-in self test (BIST) is an accepted testing approach, but its application to many designs is limited by the long test application time required to achieve high fault coverage. This work addresses the problem of BIST test time for high fault coverage by targeting test concurrency during high-level and structural synthesis. High-level synthesis generates RTL circuits which guarantee concurrent controllability and observability of all hardware components from test registers. Structural synthesis for testability completes the microarchitectural definition by specifying the test registers in the circuit, and defining a BIST test plan for the circuit. Remaining test conflicts are avoided without reducing test throughput by using partial-intrusion BIST to enable test data to be pipelined through nontest registers. The use of pipelined BIST testing in conjunction with high-level synthesis for test conflict minimization enables reduced test time through high test concurrency. Partial-intrusion BIST reduces the number of test registers by using nontest registers to propagate test data. Both behavioral and structural synthesis are directed by testability metrics which measure the test concurrency of a design. The use of these metrics in an integrated behavioral synthesis system pioneers the inclusion of test concurrency issues in microarchitectural synthesis. Experimental results using this synthesis system, SYNCBIST, show that designs generated by this approach are testable with few patterns, and using few test registers.

A high-Q bandpass fully differential SC filter with enhanced testability

Abstract: This paper presents a low-cost testing approach for switched-capacitor filters. A design for testability (DfT) methodology is discussed, and a system-level architecture is proposed providing capabilities for an off- and on-line test as well as a built-in self-test (BIST). To prove the feasibility of this approach, it has been applied to a sixth-order high-Q bandpass switched-capacitor (SC) filter. The benefit is a significant testability enhancement without degrading filter behavior. Experimental results from a silicon prototype are also presented.

Analog circuit observer blocks

Abstract: Analog and mixed-signal integrated circuits (ICs) are rapidly becoming more complex. In addition to the traditional problems associated with testing ICs, such as limited controllability and observability, analog and mixed-signal test is vulnerable to measurement induced errors. Constraints on measuring analog signals significantly increase the complexity and cost of testers for such circuits. In this paper, we introduce a design for test technique for analog and mixed-signal circuits, analog circuit observer blocks (ACOBs). ACOBs are structures designed to reduce the need for precision in measuring analog signals during circuit test. The primary technique used is that of encoding the data in the circuit (only during the test phase). ACOBs potentially offer a number of advantages over conventional off-chip test techniques such as reduced tester complexity, smaller measurement induced errors and increased observability. ACOB schemes will necessarily have to be tailored to the type of circuit targeted. We present two ACOB schemes, one for the class of fully differential circuits, the second for pipelined analog-to-digital converters. In both cases, the ACOB schemes are shown to offer substantial benefits.

H-SCAN+: a practical low-overhead RTL design-for-testability technique for industrial designs

Abstract: H-SCAN (1996) was presented as a low overhead design-for-testability strategy which is applicable to RT-level controller-data path circuits. However, from the view-point of practical use, there is a possibility that the area overhead of H-SCAN is larger than that of full-scan. Moreover, H-SCAN is unable to handle many features present in actual designs. In this paper, we propose a modified H-SCAN scheme, called "H-SCAN+", as an improved solution for actual designs. H-SCAN+ consists of several enhancements, including techniques to minimize scan design area overhead, handling of features present in actual designs, and techniques to significantly minimize the running time. We provide comprehensive results of applying H-SCAN+ to several actual RT-level designs.

A XOR-tree based technique for constant testability of configurable FPGAs

Abstract: This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and uses a two-session procedure. The approach arranges some logic blocks to be programmed as XOR-tree (or chain, or cascade) in the first session. The XOR-tree is effectively used as test vehicle for observability. The roles of the CLBs are inverted in the second session. It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished). Routing is kept local, and compatibility for a CAD implementation is also accomplished.

Testing the 400 MHz IBM generation-4 CMOS chip

Abstract: This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

On-line testing for VLSI

Abstract: A large variety of on-line testing techniques for VLSI was developed in the past and are still enriched by new developments. They can respond efficiently to the increasing complexity of VLSI circuits under the condition that available CAD tools simplify their implementation. Amongst the advanced online testing techniques are: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test, ...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components, radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1

Abstract: In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary scan, wherein the proposed DFT allows the verification of the operating frequency range of the CP-PLL while the system is in test mode. This is achieved with a minimal degradation in PLL performance, with lock characteristics remaining unchanged. Simulation results with the layout extracted netlist of the CP-PLL are used to illustrate the working of the technique.

Designing UltraSparc for testability

Abstract: With a focus on a short time to volume production, the UltraSparc microprocessor design incorporated innovative features that optimize test, debug and manufacture. The following areas are discussed: goals; cost-benefit analysis; scan design; decoded multiplexer; test generation flow; custom circuit blocks; boundary cell design; embedded array testing; and clock control features.

Integrated and automated design-for-testability implementation for cell-based ICs

Abstract: This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.

Alpha 21164 testability strategy

Abstract: A custom DFT strategy solved specific testability and manufacturing issues for this high performance microprocessor. Hardware and software assisted self test and self repair features helped meet aggressive schedule and manufacturing quality and cost goals.