Showing papers on "Design for testing published in 2001"

Test wrapper and test access mechanism co-optimization for system-on-chip

Abstract: Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SoC as well as an industrial SoC.

OPMISR: the foundation for compressed ATPG vectors

Abstract: Rapid increases in the wire-able gate counts of ASICs stress existing manufacturing test equipment in terms of test data volume and test capacity. Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors. We show compression efficiencies allowing a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests. In addition, we obtain almost a 2/spl times/ scan test time reduction. By implementing these techniques for production testing of huge-gate-count ASICs, IBM will continue using existing automated test equipment (ATE)-avoiding costly upgrades and replacements.

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Abstract: Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

Resource allocation and test scheduling for concurrent test of core-based SOC design

Abstract: A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

Bit-fixing in pseudorandom sequences for scan BIST

Abstract: A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to "fix" certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

Design of compactors for signature-analyzers in built-in self-test

Abstract: Originally developed decades ago, logic built-in self-test (BIST) evolved and is now increasingly being adopted to cope with rapid growth in design size and complexity. Compared to deterministic pattern test, logic BIST requires many more test patterns, and therefore, increased test time unless many more internal scan chains can be shifted in parallel. To match this large number of scan chains, the width of the signature analyzer would have to be enlarged, which would result in large area overhead and signature storage space. Instead, a combinational space-compactor is inserted between the scan chain outputs and the signature analyzer inputs. However, the compactor may deteriorate the ability to test and diagnose the design. This paper analyzes how compactors affect test and diagnosis and shows that compactors can be designed to actually improve the testability of certain faults, while providing full diagnosis capability. Algorithms that allow automated design of optimal compactors are presented and results are discussed.

Enhanced reduced pin-count test for full-scan design

Abstract: This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.

Limitations and challenges of computer-aided design technology for CMOS VLSI

Abstract: As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation.

An integrated system-on-chip test framework

Abstract: In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

Switching activity generation with automated BIST synthesis for performance testing of interconnects

Abstract: A novel scheme of synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary of the component of a system under test to generate interconnect switching activities that resemble real life interconnect switching profiles is proposed. The goal is to perform at-speed interconnect test while simultaneously capturing the dynamic switching effects such as crosstalk and ground bounce, as accurately as possible during interconnect built-in self-test. A library of nonlinear feedback shift register structures called precharacterized test pattern generators (P-TPGs) is constructed. Components of P-TPGs can be modeled using Markov chain and can be interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. The unique advantage of this scheme is that there is no simulation overhead since P-TPG components are precharacterized by solving Markov equations analytically. An integrated genetic algorithm-based search and optimization technique for finding the best P-TPG component among various possible implementations and matching its activity profiles with those of the interconnections under test has been designed and implemented synthesis for testability allows generation of the worst case interconnect switching activities. Experimental results confirm the validity of our approach.

Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip

Abstract: Decreasing feature sizes and increasing customer demand for more functionality have forced design teams to re-use design blocks and application platforms. As a result, re-use of test, design-for-test and design-for-debug for large system chips is becoming increasingly important and increasingly necessary.. In this paper, the test and debug features of the Nexperia/sup TM/ PNX8525 chip are presented. The PNX8525 chip is a large system chip for the consumer electronics market. The impact of core-based testing is discussed, at both the core-level and the top-level, together with the design-for-debug implementation on this multiple clock domain chip.

Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

Abstract: The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. This paper reports new space compression techniques which facilitate designing such circuits using compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The compaction techniques utilize the concepts of Hamming distance, sequence weights, and derived sequences in conjunction with the probabilities of error occurrence in the selection of specific gates for merger of a pair of output bit streams from the CUT. The outputs of the space compactor may eventually be fed into a time compactor (viz. syndrome counter) to derive the CUT signatures. The proposed techniques guarantee simple design with a very high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with numerous examples. Specifically, extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST programs confirm the usefulness of the suggested approaches.

Instruction-level DFT for testing processor and IP cores in system-on-a-chip

Abstract: Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination of dedicated test circuitry and better power and thermal management during testing, However, such a self-test strategy might require a lengthy test program and might not achieve a high enough fault coverage. We propose a DfT methodology to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core. This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance overhead. The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the program runtime, as compared to the case without instruction-level DfT.

IS-FPGA : a new symmetric FPGA architecture with implicit scan

Abstract: Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

TAO: regular expression-based register-transfer level testability analysis and optimization

Abstract: In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable.

Constructing self-testable software components

Abstract: Component-based software engineering techniques are gaining substantial because of their potential to improve productivity and lower development costs of new software applications, yet satisfying high reliability requirements. A first step to address such high reliability requirements consists in reusing reliable components. To merit the attribute "reliable", a component should be extensively validated. As far as testing is the technique most commonly used for validation, this means that reusable components should well tested. For tests to be applied efficiently and on time, a component should be testable. This paper presents an approach to improve component testability by integrating testing resources into it, and hence obtaining a self-testable component. A prototyping tool, Concat, was developed to support the proposed approach. The tool is intended for OO components implemented in C++. Some preliminary results of an empirical evaluation of the fault detection effectiveness of the proposed testing approach are also discussed.

Testability implications in low-cost integrated radio transceivers: a Bluetooth case study

Abstract: As the use of wireless communications in daily life increases, attaining low-cost solutions becomes increasingly important due to shrinking profit margins. Cost optimization that solely targets at minimization of the cost of system architecture may result in suboptimal, highly untestable, solutions. Test design and design for testability need to be incorporated into the system design flow to achieve viable solutions. This paper presents an analysis of test requirements, implications and test cost for low-cost Bluetooth systems. Testability problems are identified and possible solutions along with avenues to reduce the test cost by utilizing lower-cost testers are discussed.

Very low cost testers: Opportunities and challenges

Abstract: Prudent application of design-for-testability guidelines can yield designs that don't require all the expensive features of traditional automated test equipment. The authors describe how the VLSI design and semiconductor test communities can cooperate to greatly reduce testing costs.

On RTL scan design

Abstract: This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

A practical built-in current sensor for I/sub DDQ/ testing

Abstract: This paper describes a new built-in current sensor (BICS) design, comprised of a MAGFET current sensor, stochastic sensor, self-calibration tool, counter, and scan chain. By indirectly measuring the current, the sensor avoids the unacceptable drawbacks of past BICS designs. Test chips fabricated in 180 nm and 250 nm technology demonstrate that the sensor can be used for IDDQ testing of large, high-performance, deep submicron circuits. This sensor should extend practical IDDQ testing to the 35 nm technology generation.

DFT for high-quality low cost manufacturing test

Abstract: The semiconductor industry is capable of building "tester-limited fabs" and definitely needs a more cost-effective solution for the cost of test problem than the one we have today. The solutions are likely, to come from several different sources. While the ATE industry is addressing the cost of test problem by designing new DFT testers, it is the EDA industry that holds the key to providing an embedded test solution that guarantees high-quality, low cost manufacturing test. In this presentation we examine various DFT technologies and their ability to provide high quality low cost manufacturing test.

Rxiensing scan chains for test pattern decompression

Abstract: The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

Fast test generation for circuits with RTL and gate-level views

Abstract: In this paper, we propose a simple two-pass strategy that couples register-transfer level (RTL) test generation with gate-level sequential test generation through fault lists. We motivate this approach by showing that faults found hard-to-test by gate-level sequential test generators are often easily testable at the RTL. Likewise, modules found symbolically untestable at the RTL have many of their faults testable at the gate level. Therefore, a two-pass strategy, which runs a fast RTL test generator followed by a gate-level sequential test generator on the remaining untested faults, can leverage off the strengths of each test generator. No modifications are necessary to the source code of either test generator to make this approach work. This makes it particularly attractive to industrial test flows, where the available gate-level test generator may be from a commercial vendor. This is in contrast to many hierarchical test generation techniques where there is significant interdependence between test generation at the register transfer and gate levels. For several benchmark circuits, we experimentally studied the performance of the two-pass approach using a symbolic RTL test generator, TAO, and efficient gate-level test generators, HITEC and SEST. Experimental results show that the proposed two-pass approach achieves a maximum speedup of 103X over a single-pass gate-level sequential test generator. The average speedup was 38X. No design for testability modifications were assumed for the circuits.

Closing the gap between analog and digital testing

Abstract: This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.

An on-chip march pattern generator for testing embedded memory cores

Abstract: In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead.

On-chip test of the shift register for high-end network switch based on cell-based design

Abstract: We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

A building block BIST methodology for SOC designs: a case study

Abstract: System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems.

Configuration free SoC interconnect BIST methodology

Abstract: Three-state drivers are modified to exhibit wired-logic properties in test mode. It does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

The design and optimization of SOC test solutions

Abstract: We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.

Design for hierarchical two-pattern testability of data paths

Abstract: Introduces the concept of hierarchical testability, of data paths for delay faults. A definition of a hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide similar advantages to the enhanced scan approach at the cost of much lower hardware overhead.