Showing papers on "Design for testing published in 2002"

Embedded deterministic test for low cost manufacturing test

Abstract: This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Managing power and performance for system-on-chip designs using Voltage Islands

Abstract: This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption. Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

X-compact: an efficient response compaction technique for test cost reduction

Abstract: We present a technique for compacting test response data using combinational logic circuits. Our compaction technique enables up to an exponential reduction in the number of pins required to collect test response from a chip. The combinational circuits require negligible area, do not add any extra delay during normal operation, guarantee detection of defective chips even in the presence of sources of unknown logic values (often referred to as Xs) and preserve diagnosis capabilities for all practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test data volume, test-I/O pins and tester channels, and also to improve test quality.

A Designer’s Guide to Built-In Self-Test

Abstract: Preface. About the Author. 1. An Overview of BIST. 2. Fault Models, Detection, and Simulation. 3. Design for Testability. 4. Test Pattern Generation. 5. Output Response Analysis. 6. Manufacturing and System-Level Use of BIST. 7. Built-In Logic Block Observer. 8. Pseudo-Exhaustive BIST. 9. Circular BIST. 10. Scan-Based BIST. 11. Non-Intrusive BIST. 12. BIST for Regular Structures. 13. BIST for FPGAs and CPLDs. 14. Applying Digital BIST of Mixed-Signal Systems. 15. Merging BIST and Concurrent Fault Detection. Acronyms. Bibliography. Index.

Effective and efficient test architecture design for SOCs

Abstract: This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE vector memory depth and test application time. In this paper, we formulate the problems of test architecture design both for modules with fixed- and flexible-length scan chains. Subsequently, we derive a formulation of an architecture-independent test time lower bound for SOCs and list the lower bound values for the 'ITC'02 SOC test benchmarks'. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and testrail architectures with serial and parallel test schedules. Experimental results for the 'ITC'02 SOC test benchmarks' show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.

Extending OPMISR beyond 10/spl times/ scan test efficiency

Abstract: Rapidly increasing ASIC gate counts are stressing the test capacity of manufacturing test equipment. New on-product multiple-input signature register (OPMISR) techniques compress test vectors produced by ATPG, substantially reducing data volume and test time.

Multiscan-based test compression and hardware decompression using LZ77

Abstract: In this paper we present a new test data compression technique and an associated decompression scheme for testing VLSI chips. Our method is based on our novel use of the much utilized, in software, LZW, particularly LZ77 algorithm. We adapt LZ77 to accommodate bit strings rather than character sets. Moreover, we exploit the large presence of don't cares in the uncompressed test sets that we generated using commercial ATPG tools. Our decompression scheme makes effective use of the on chip boundary scan during decompression and then feeding the internal multiple scan chains for testing. The hardware overhead cost for this scheme is minimal. Experimental results are provided.

Efficient Wrapper/TAM Co-Optimization for Large SOCs

Abstract: Core test wrappers and test access mechanisms (TAMs) are important components of a system-on-chip (SOC) test architecture. Wrapper/TAM co-optimization is necessary to minimize the SOC testing time. Most prior research in wrapper/TAM design has addressed wrapper design and TAM optimization as separate problems, thereby leading to results that are sub-optimal. We present a fast heuristic technique for wrapper/TAM co-optimization, and demonstrate its scalability for several industrial SOCs. This extends recent work on exact methods for wrapper/TAM co-optimization based on integer linear programming and exhaustive enumeration. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to the testing times obtained using exact methods. Moreover more than two orders of magnitude reduction can be obtained in the CPU time compared to exact methods. Furthermore, we are now able to design efficient test access architectures with a larger number of TAMs.

Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell

Abstract: A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional test techniques. We have shown how to modify the basic concept of OBT to come up with a practical method. Using our approach, designers can use OBT to pave the way for future developments in SoC testing, and it is simple to extend this idea to BIST.

Using embedded FPGAs for SoC yield improvement

Abstract: In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC. We present methods for testing, diagnosing, and repairing embedded FPGAs, for which complete testability is achieved without any area overhead or performance degradation. We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with a low-cost tester.

A new look at hardware maze routing

Abstract: This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines their design to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing. An RTL implementation has been developed for this design in VHDL, and initial results show promise for its realization using ASIC, custom, or FPGA technology.

A high-throughput low-cost AES cipher chip

Abstract: We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 /spl mu/m CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

Cluster-based test architecture design for system-on-chip

Abstract: A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Architectures. An important characteristic of the TestRail Architecture is that it allows for efficient testing of both the cores as well as the core-external circuitry. We present two alternative optimization algorithms for the TestRail Architecture, that minimize the total core-internal test time of the cores in the SOC. These algorithms handle both cores with fixed-length and flexible-length scan chains. Experimental results on three industrial benchmark SOCs show that, compared to previous publications, we obtain comparable or better test times at drastically reduced compute times.

Multiple scan chains for power minimization during test application in sequential circuits

Abstract: The paper presents a novel technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed design for test architecture is based on classifying scan latches into compatible, incompatible and independent scan latches. Based on their classification, the scan latches are partitioned into multiple scan chains and a single extra test vector associated with each scan chain is computed. A new test application strategy which applies the extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. The newly introduced multiple scan chain-based technique does not introduce performance degradation and minimizes clock tree power dissipation with minimal impact on both test area and test data overhead. Unlike previous approaches which are test set dependent, and hence are not able to handle large circuits due to the complexity of the design space, the paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large test sets. For example, in the case of the benchmark circuit s15850, it takes <6009 in computational time and <1 percent in test area and test data overhead to achieve over 80 percent savings in power dissipation.

Modeling the economics of testing: a DFT perspective

Abstract: Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy's impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT's impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don't consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies.

High-level and hierarchical test sequence generation

Abstract: Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.

A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

Abstract: An emerging trend in microprocessor architecture for servers is to design chips with multiple processor cores on a chip called chip multi-processors (CMPs). Due to the short design cycle time and large size of these chips, the design-for-testability and testing of such chips is a major challenge. In this paper we describe a hierarchical DFT architecture for UltraSPARC/spl trade/ CMPs that is scalable with number of processor cores and can be implemented in a very short design cycle time. The DFT architecture allows testing of the processor cores individually for diagnosis as well as concurrently to reduce test application time and thus test cost. The DFT architecture can be easily ported across CMPs with different numbers of processor cores as well as to higher order CMPs designed by putting together CMPs.

Test bus sizing for system-on-a-chip

Abstract: System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.

Dynamic scan: driving down the cost of test

Abstract: Two factors primarily drive the soaring cost of semiconductor test: the number of test patterns applied to each chip and the time it takes to run each pattern. Typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns. These tests are applied through scan chains that operate at about 25 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It's easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the well-established scan test methodology. The authors initial studies indicate that dynamic scan could easily reduce the time spent applying test patterns by 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.

Native mode functional self-test generation for Systems-on-Chip

Abstract: With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor's instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.

Test Planning and Design Space Exploration in a Core-Based Environment

Abstract: This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the consideration of different optimization factors (area, ping and test time) during the global TAM and test schedule definition. This expansion of concerns makes possible an efficient yet fine-grained search in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test design.

Re-using DFT logic for functional and silicon debugging test

Abstract: This paper presents a technique of re-using DFT logic for system functional and silicon debugging. By re-configuring the existing DFT logic implemented on an ASIC, we are able to 1) test each part of an ASIC in a system environment separately and thus locate manufacturing defects, 2) control and observe any state elements of an ASIC to facilitate system function and silicon debugging, and 3) use structural tests to cover device and their interconnect tests on a board. Therefore, we can achieve debugging and test at both device level and system board level.

Scan test data volume reduction in multi-clocked designs with safe capture technique

Abstract: As a result of increasing design size and complexity, the multiple clock domain design style has become a new trend in the industry. Several techniques to test circuits with multiple clocks are known; however, they often result in increased test time and tester memory for large and complex circuits. This paper presents a strategy to reduce the test pattern count during ATPG by forcing a safe capture behavior when multiple clocks are applied during capture. The usage of multiple clocks allows additional observability, which can significantly reduce the pattern count for circuits with many clocks. Experimental results indicate that proposed strategy results in larger and moreover, more consistent reduction in test sizes.

Program slicing for hierarchical test generation

Abstract: Sequential Automatic Test Pattern Generation (ATPG) is extremely computation intensive and produces good results only on relatively small designs. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical ATPG which targets one module at a time and abstracts the rest of the design. The technique for obtaining a "constraint slice" for each embedded Module Under Test (MUT) within a design is described in detail. The technique has been incorporated in an automated tool for designs described in Verilog, and results on large benchmark circuits show the significant benefits of the approach.

Conformance test experiments for distributed real-time systems

Abstract: This paper introduces a new technique for testing that a distributed real-time system satisfies a formal timed automata specification. It outlines how to write test specifications in the language of Uppaal timed automata, how to translate those specifications into program code for executing the tests, and describes the results of test experiments on a distributed real-time system with limited hardware and software resources.

Multilevel testability analysis and solutions for integrated Bluetooth transceivers

Abstract: As use of wireless communications rises and profit margins shrink, low-cost solutions are becoming increasingly important. Incorporating test design and DFT into the system design flow is essential to achieving such solutions. This case study analyzes test requirements, implications, and test cost for low-cost Bluetooth systems, which enable communication among several electronic components.

Enhanced Reduced Pin-Count Test for Full-Scan Design

Abstract: This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

Recent advances in test planning for modular testing of core-based SOCs

Abstract: Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures An extensive list of references to prior and current work in the SOC test planning domain is included

Circular BIST with state skipping

Abstract: Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.

Adding synchronous and LSSD modes to asynchronous circuits

Abstract: A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.