Showing papers on "Design for testing published in 2005"

Robust system design with built-in soft-error resilience

Abstract: Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

Secure scan: a design-for-test architecture for crypto chips

Abstract: Scan-based design-for-test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip thus compromising its security. On one hand, sacrificing security for testability by using traditional scan-based DFT restricts its use in privacy sensitive applications. On the other hand, sacrificing testability for security by abandoning scan-based DFT hurts product quality. The security of a crypto chip comes from the small secret key stored in a few registers and the testability of a crypto chip comes from the data path and control path implementing the crypto algorithm. Based on this key observation, we propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security. We used a hardware implementation of the advanced encryption standard (AES) to show that the traditional scan DFT scheme can compromise the secret key. We then showed that by using secure scan DFT, neither the secret key nor the testability of the AES implementation is compromised.

A scalable test strategy for network-on-chip routers

Abstract: Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

Test control for secure scan designs

Abstract: Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security vulnerability. In this paper, we propose to merge security requirements with testability ones in a control-oriented design for security scan technique.

Finite memory test response compactors for embedded test applications

Abstract: This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.

Fault diagnosis of analog integrated circuits

Abstract: Fault and Fault Modelling.- Test Stimulus Generation.- Fault Diagnosis Methodology.- Design for Testability and Built-In Self-Test.

A new diagnosis approach for handling tolerance in analog and mixed-signal circuits by using fuzzy math

Abstract: A novel analysis method for analog circuits test and diagnosis is described in this paper. Diagnosis hypotheses are represented and fuzzy math is used to express the diagnosis hypotheses and strategy. Based on it, new equivalent fault model is presented and used for test node selection and design for test. Especially, parametric fault test for linear analog circuits with tolerance analysis is presented using both sensitivity method and fuzzy analysis method.

Rescue: A Microarchitecture for Testability and Defect Tolerance

Abstract: Scaling feature size improves processor performance but increases each deviceýs susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve significantly to maintain yields. Redundancy techniques in memory have been successful at improving yield in the presence of defects. Apart from core sparing which disables faulty cores in a chip multiprocessor, little has been done to target the core logic. While previous work has proposed that either inherent or added redundancy in the core logic can be used to tolerate defects, the key issues of realistic testing and fault isolation have been ignored. This paper is the first to consider testability and fault isolation in designing modern high-performance, defect-tolerant microarchitectures. We define intra-cycle logic independence (ICI) as the condition needed for conventional scan test to isolate faults quickly to the microarchitectural-block granularity. We propose logic transformations to redesign conventional superscalar microarchitecture to comply with ICI. We call our novel, testable, and defect-tolerant microarchitecture Rescue. We build a verilog model of Rescue and verify that faults can be isolated to the required precision using only conventional scan test. Using performace simulations, we show that ICI transformations reduce IPC only by 4% on average for SPEC2000 programs. Taking yield improvement into account, Rescue improves average yield-adjusted instruction throughput over core sparing by 12% and 22% at 32nm and 18nm technology nodes, respectively.

Progressive random access scan: a simultaneous solution to test power, test data volume and test time

Abstract: Traditional testing research for testing VLSI circuits has been confined to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However, there has been a paradigm shift in the cost factor - the transistor cost has been dropping exponentially whereas the test cost is starting to increase. We believe that adding marginally more hardware is acceptable provided the test cost can be reduced considerably. This paper takes such a view of testing and rejuvenates the random access scan as a design for testability method that simultaneously addresses three limitations of the traditional serial scan namely, test data volume, test application time, and test power. The novelty of the progressive random access scan approach proposed in this paper lies in developing the test architecture and formulating the test application time and test data volume reduction problems. We provide a traveling salesman formulation of these problems in our test architecture setting. Experimental results show the practicality of our approach as the hardware cost components, consisting of routing and transistor count, increase only marginally compared to the serial scan approach whereas there is a dramatic decrease in test power consumption (nearly a 1000 fold decrease in average test power) as well as the test data volume and the test times are halved

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Abstract: This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

Logic soft errors: a major barrier to robust platform design

Abstract: Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques

Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

Abstract: In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.

Jump scan: a DFT technique for low power testing

Abstract: This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by two thirds compared with the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability methodology and needs no extra computation. The penalties are area overhead and speed degradation.

Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

Abstract: Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets T/sub UTS/ such that each C(n) has a unique test set T(n) in T/sub UTS/ that detects all F-type faults in every member of C(n). We show that if k /spl ges/ 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n/sup 2/ + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.

Testability features of the first-generation CELL processor

Abstract: The first generation CELL processor presented a test challenge in that the chip incorporated multiple processing elements, several multi-gigahertz synchronous and asynchronous clock domains, and many custom design elements. The test objective for the CELL design was to have high test coverage and a small test time. In addition to the objectives mentioned above, the CELL test logic is designed to support a modular design point and support for partial good processing elements. This paper will give an overview of the manufacturing test elements that were designed into the CELL processor

Integrated Circuit Test Engineering: Modern Techniques

Abstract: to Integrated Circuit Test Engineering.- Fabrication Processes for Integrated Circuits.- Digital Logic Test.- Memory Test.- Analogue Test.- Mixed-Signal Test.- Input-Output Test.- Design for Testability - Structured Test Approaches.- System on a Chip (SoC) Test.- Test Pattern Generation and Fault Simulation.- Automatic Test Equipment (ATE) and Production Test.- Test Economics.

Introduction to Advanced System-on-Chip Test Design and Optimization

Abstract: Testing ofIntegrated Circuits is important to ensure the production offault-free chips. However, testing is becoming cumbersome andexpensive due to the increasing complexity of these ICs. Technologydevelopment has made it possible to produce chips where a completesystem, with an enormous transistor count, operating at a highclock frequency, is placed on a single die - SOC (System-on-Chip).The device size miniaturization leads to new fault types, theincreasing clock frequencies enforces testing for timing faults,and the increasing transistor count results in a higher number ofpossible fault sites. Testing must handle all these new challengesin an efficient manner having a global system perspective.Test design is applied to make a system testable. In a modularcore-based environment where blocks of reusable logic, the socalled cores, are integrated to a system, test design for each coreinclude: test method selection, test data (stimuli and responses)generation (ATPG), definition of test data storage and partitioning[off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST(Built-In Self-Test)], wrapper selection and design (IEEE std1500), TAM (test access mechanism) design, and test schedulingminimizing a cost function whilst considering limitations andconstraint. A system test design perspective that takes all theissues above into account is required in order to develop aglobally optimized solution.SOC test design and its optimization is the topic of this book. Itgives an introduction to testing, describes the problems related toSOC testing, discusses the modeling granularity and theimplementation into EDA (electronic design automation) tools. Thebook is divided into three sections: i) test concepts, ii) SOCdesign for test, and iii) SOC test applications. The first partcovers an introduction into test problems including faults, faulttypes, design-flow, design-for-test techniques such as scan-testingand Boundary Scan. The second part of the book discusses SOCrelated problems such as system modeling, test conflicts, powerconsumption, test access mechanism design, test scheduling anddefect-oriented scheduling. Finally, the third part focuses on SOCapplications, such as integrated test scheduling and TAM design,defect-oriented scheduling, and integrating test design with thecore selection process. (Less)

Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems

Abstract: Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by high speed, large scale implementation of SerDes I/Os (serial/deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper, we present the test challenges and describe on-chip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets

An integrated debugging environment for reprogrammble hardware systems

Abstract: Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow.

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

Abstract: With increasing inter-die and intra-die parameter variations in sub-100-nm process technologies, new failure mechanisms are emerging in CMOS circuits. These failures lead to reduction in reliability of circuits, especially the area-constrained SRAM cells. In this paper, we have analyzed the emerging failure mechanisms in SRAM caches due to transistor V/sub t/ variations, which results from process variations. Also we have proposed solutions to detect those failures efficiently. In particular, in this work, SRAM failure mechanisms under transistor V/sub t/ variations are mapped to logic fault models. March test sequences have been optimized to address the emerging failure mechanisms with minimal overhead on test time. Moreover, we have proposed a design for test circuit to complement the March test sequence for at-speed testing of SRAMs. The proposed technique, referred as double sensing, can be used to test the stability of SRAM cells during read operations. Using the proposed March test sequence along with the double sensing technique, a test time reduction of 29% is achieved, compared to the existing test techniques with the same fault coverage. We have also demonstrated that double sensing can be used during SRAM normal operation for online detection and correction of any number of random read faults.

Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

Abstract: Multi-site testing is a popular and effective way to increase test throughput and reduce test costs The authors pro\pose a test flow with large multi-site testing during wafer test, enabled by a narrow SOC-ATE test interface, and relatively small multi-site testing during final (packaged-IC) test, in which all SOC pins need to be contacted They present a throughput model for multi-site testing, valid for both wafer test and final test, which considers the effects of test time, index time, abort-on-fail and re-test after contact fails Conventional multi-site testing requires sufficient ATE channels to allow testing of multiple SOCs in parallel Instead, a given fixed ATE is assumed, and for a given SOC they design and optimise the on-chip design-for-test infrastructure, in order to maximise the throughput during wafer test The on-chip DfT consists of an E-RPCT wrapper, and, for modularly tested SOCs, module wrappers and TAMs Subsequently, for the designed test infrastructure, they also maximise the test throughput for final test by tuning its multi-site number Finally, they present experimental results for the ITC'02 SOC Test Benchmarks and a complex Philips SOC

Word line pulsing technique for stability fault detection in SRAM cells

Abstract: Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

Segmented addressable scan architecture

Abstract: This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.

Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Abstract: In recent years, several electronic design automation (EDA) problems in testing and verification have been formulated as Boolean satisfiability (SAT) instances due to the development of efficient general-purpose SAT solvers. Problem-specific learning techniques and heuristics can be integrated into the SAT solver to further speed-up the search for a satisfying assignment. In this paper, we target the problem of generating a complete test-suite for the path delay fault (PDF) model. We provide an incremental satisfiability framework that learns from (1) static logic implications, (2) segment-specific clauses, and (3) unsatisfiability cores of each untestable partial PDF. These learning techniques improvise the test generation for path delay faults that have common testable and/or untestable segments. The experimental results show that a significant portion of PDFs can be excluded dynamically in the proposed incremental SAT formulation for large benchmark circuits, thus potentially achieving speed-ups for PDF test generation.

IEEE 1500 utilization in SOC design and test

Abstract: Integrating numerous IP cores into a SoC design is a complex activity from the design-for-testability point of view. Also, accessing and exercising test and diagnosis patterns on each IP core during the manufacturing phases is a major challenge. Designing the IEEE 1500 standard into the IP core and leveraging it during the DFT integration and manufacturing phases drastically simplify these challenges. This paper demonstrates the use of IEEE 1500 in embedded memory IP cores, and describes how it can be leveraged in a SoC during its design and manufacturing phases

Power-scan chain: design for analog testability

Abstract: This paper reports a design for testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the core's power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. In this paper, we further provide experimental evidence of our approach as applied to an RF device

Test power reductions through computationally efficient, decoupled scan chain modifications

Abstract: SOC test time minimization hinges on the attainment of core test parallelism; yet test power constraints hamper this parallelism as excessive power dissipation may damage the SOC being tested. We propose a test power reduction methodology for SOC cores through scan chain modification. By inserting logic gates between scan cells, a given set of test vectors & captured responses is transformed into a new set of inserted stimuli & observed responses that yield fewer scan chain transitions. In identifying the best possible scan chain modification, we pursue a decoupled strategy wherein test data are decomposed into blocks, which are optimized for power in a mutually independent manner. The decoupled handling of test data blocks not only ensures significantly high levels of overall power reduction but it furthermore delivers computational efficiency at the same time. The proposed methodology is applicable to both fully, and partially specified test data; test data analysis in the latter case is performed on the basis of stimuli-directed controllability measures which we introduce. To explore the tradeoff between the test power reduction attained by the proposed methodology & the computational cost, we carry out an analysis that establishes the relationship between block granularity & the number of scan chain modifications. Such an analysis enables the utilization of the proposed methodology in a computationally efficient manner, while delivering solutions that comply with the stringent area & layout constraints in SOC as well.

Yield enhancement through fast statistical scan test analysis for digital logic

Abstract: To enable fast technology ramp up and stable high yield a good understanding and fast detection of yield detractors is required. This paper focuses on fast statistical analysis of failures in the logic circuit part of SOC's, especially during ramp-up of a new product or technology. The failing chips response to the production test program is the key for a statistical search for systematic yield losses. The scan test method allows diagnosing the failing circuit nodes in the logic based on the chips misbehavior. Intelligent processing and analysis of this information enables identification of important yield detractors. A description of the approach and experimental results are provided

Low Power Test Compression Technique for Designs with Multiple Scan Chain

Abstract: This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs It can also help to reduce test time and tester channel requirements with small hardware overhead In the proposed approach, we start with a pre-computed test cube set and fill the don’t-cares with proper values for joint reduction of test data volume and scan power consumption In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression Experimental results for the larger ISCAS’89 benchmarks show the efficiency of the proposed technique