Showing papers on "Design for testing published in 2006"

VLSI Test Principles and Architectures: Design for Testability

Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age

Secure Scan: A Design-for-Test Architecture for Crypto Chips

Abstract: Scan-based design for test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip, thus compromising its security. On one hand, sacrificing the security for testability by using a traditional scan-based DFT restricts its use in privacy sensitive applications. On the other hand, sacrificing the testability for security by abandoning the scan-based DFT hurts the product quality. The security of a crypto chip comes from the small secret key stored in a few registers, and the testability of a crypto chip comes from the data path and control path implementing the crypto algorithm. Based on this key observation, the authors propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security. They used a hardware implementation of the advanced encryption standard to show that the traditional scan DFT scheme can compromise the secret key. They then showed that by using secure-scan DFT, neither the secret key nor the testability of the AES implementation is compromised

Design for Testability

Abstract: Publisher Summary This chapter discusses design for testability (DFT) techniques for testing modern digital circuits These DFT techniques are required in order to improve the quality and reduce the test cost of the digital circuit, while at the same time simplifying the test, debug and diagnose tasks The chapter also investigates that whether a design is implemented in a test-friendly manner and to recommend changes in order to improve the testability of the design for achieving the goals It also identifies scan design rule violations and understands the basics for successfully converting a design into a scan design This chapter describes the basic DFT concepts and methods for performing testability analysis It also briefly discusses DFT techniques, scan design, and DFT methodology including popular scan cell designs, scan architectures, scan design rules, scan design flow, and special-purpose scan designs Finally, advanced DFTtechniques for use at the register-transfer level (RTL) are presented in order tofurther reduce DFT design iterations and test development time

At-Speed Structural Test For High-Performance ASICs

Abstract: At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing

Abstract: In order to reduce production costs of RF devices, it is important to remove bad circuits very early in the production flow. It is all the more true for dies designed to be integrated in complex systems. Thus highly efficient RF wafer testing is mandatory for those applications to prevent the loss of assembled systems due to defective RF dies. The problem is that current RF probing technologies hardly fulfill the industrial test requirements in terms of accuracy, reliability and cost. The proposed method proves to be a very interesting alternative to validate RF parameters with no need of expensive RF equipments (RF probes and RF automated test equipments (ATE)). A new test strategy based on DC or very low frequency (LF) measurements, which allows the elimination of expensive RF tests, is presented. The main idea is to insert some simple design for test (DfT) circuitry within the chip. This DfT provides relevant information on the structural behavior of the device blocks. The internal node data are additional to standard DC test measurements like power supply current or advanced DC test signatures (e.g. Vdd ramping), and LF measurements like gain in loopback mode. Since RF performance of each block is directly related to such structural data, it is possible to predict the RF characteristics of the blocks without time consuming RF measurements. RF parameters estimation is performed using nonlinear Artificial Neural Networks.

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Abstract: Overheating has been acknowledged as a major problem during the testing of complex system-on-chip integrated circuits. Several power-constrained test-scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the nonuniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test-scheduling approach that is able to produce short test schedules and guarantee thermal safety at the same time. Two thermal-safe test-scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test-scheduling algorithm may not be feasible. Based on a low-complexity test-session thermal-cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm

EDA for IC System Design, Verification, and Testing

Abstract: Introduction. The IC Design Process and EDA. Tools and Methodologies for System-Level Design. System-level specification and modeling languages. SoC Block Based Design and IP Assembly. Performance Evaluation Methods for MPSoC Design. Processor Modeling and Design Tools. Embedded Software Modeling and Design. Using Performance Metrics to Select Microprocessor Cores for IC Designs. Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis. Cycle-Accurate System-Level Modeling and Performance Evaluation. Micro-Architectural Power Estimation and Optimization. Design Planning. Design and Verification Languages. Digital Simulation. Using Transactional Level Models in a SoC Design Flow. Assertion-based verification. Hardware Acceleration and Emulation. Formal Property Verification. Design for Test. Automatic Test Pattern Generation. Analog and Mixed-Signal Test.

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

Abstract: We present an approach to prevent over testing in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of over testing in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between over testing prevention and test compression

An External Test Approach for Network-on-a-Chip Switches

Abstract: Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose Designfor- Testability (DfT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults, opens and shorts between adjacent interconnection lines are covered by the method. The approach allows to reach higher fault coverages in comparison to the recent DfT based solutions.

A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing

Abstract: The performance of high-speed serial data links, along with the architectures of the transmitter and receiver circuitry used on either end, has led to increasing difficulty in applying traditional test and measurement techniques to characterize these channels. One solution, explored in this work, utilizes stimulus generation and response analysis circuitry embedded in the devices driving and receiving the links to perform a variety of tests and measurements that match and even exceed those possible with traditional instruments, as actual silicon results demonstrate. The access to this embedded measurement circuitry is provided via the IEEE Std. 1149.1 Test Access Port by use of a possible prototype for the draft IEEE P1687 (IJTAG) standard. This access mechanism is explained and its wider applications for test and debug are explored.

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Abstract: Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip

System-on-chip test scheduling with reconfigurable core wrappers

Abstract: The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.

Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation

Abstract: This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low-level simulation models. Traditionally, alternate test makes use of circuit and process-level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a "gray-box" approach by creating a high-level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front-end chip, for which 13 specifications including S-parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy.

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Abstract: Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan (Whetsel, 2000) and (Lee et al., 2004) has been shown to be an effective technique in addressing test power issues in industrial designs (Saxena et al., 2001). To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%

Software-Based Self-Test of Processors under Power Constraints

Abstract: Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initialization tests for the whole system. In this paper, for the first time a structural SBST methodology is proposed which optimizes energy, average power consumption, test length and fault coverage at the same time.

A DFT Approach for Testing Embedded Systems Using DC Sensors

Abstract: In this article, we propose a sensor-based BIT scheme By using sensors, we mitigate any issues related to signal integrity and diversity in the test response capture process Also, BIT can provide a test framework to estimate specifications during production testing for various modules in a heterogeneous SoC or SiP This scheme involves designing sensors for each module directly into the device under test (DUD and capturing sensor outputs that are low-frequency DC signals A low-frequency mixed-signal tester can capture these sensor responses, analyze them to infer each specific module's performance, and determine the overall pass-fail decision for the DUT The embedded sensors perform the necessary signal conditioning of the DUT output signals, thereby significantly reducing the ATE's response capture and analysis overhead As an example, it's possible to test a digital module for rise time by incorporating an integrator at the output node as a sensor As the output node voltage increases, the integrator's output capacitance charges to a DC value The ATE samples the capacitor's DC voltage at a specific time, and the DC voltage would be proportional to the DUT's rise time In this case, there would be no need to sample the rising waveform, and the ATE's digitizer requirements could be significantly relaxed This example indicates that during production testing, carefully chosen sensors can effectively simplify the overall test procedure

Fast detection of data retention faults and other SRAM cell open defects

Abstract: Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

Using UML activities for system-on-chip design and synthesis

Abstract: The continuous advances in manufacturing Integrated Circuits (ICs) enable complete systems on a single chip. However, the design effort for such System-on-Chip (SoC) solutions is significant. The productivity of the design teams currently lags behind the advances in manufacturing and this design productivity gap is still widening. One important reason is the lack of abstraction in traditional Hardware Description Languages (HDLs) like VHDL. The UML provides more abstract concepts for modeling behavior that can also be employed for hardware design. In particular, the new UML Activity semantics fit nicely with the inherent data flow in hardware systems. Therefore, we introduce a UML-based design approach for complete SoC specification. Our approach enables generation of complete synthesizable HDL code. The equivalent hardware can be automatically generated using the existing tools chains. As an example, we outline Handel-C code generation for an MP3 decoder design.

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size

Abstract: The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications

Abstract: An otherwise well-known ratiometric Built-In Current Sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a Low-Noise Amplifier (LNA). Measurements confirm the BICS’s low sensitivity to process variations and its transparency relative to the circuit under test (CUT).

DFT infrastructure for broadside two-pattern test of core-based SOCs

Abstract: Existing approaches for modular manufacturing test of core-based system-on-a-chip (SOC) devices do not provide any explicit mechanism for delivering two-pattern tests in the broadside mode, which is necessary to achieve reliable coverage of delay and stuck-open faults. Although wrapper input cells can be enhanced with two memory elements to address this problem, this incur a large test area overhead. This paper proposes a novel architecture for broadside two-pattern test of core-based SOCs without any loss in fault coverage and without increasing the size of the wrapper input cells. The proposed solution combines the dedicated bus-based test access mechanism and functional interconnects for test data transfer in order to provide full controllability of the wrapper input cells in the two consecutive clock cycles required by two-pattern testing. New algorithms for test access mechanism design and test scheduling are proposed and design trade-offs between test area and testing time are discussed using experimental results.

A network security processor design based on an integrated SOC design and test platform

Abstract: In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18 /spl mu/m CMOS technology. The chip area is 5 mm /spl times/ 5 mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80 MHz. The best performance of the crypto-engines is 1.025 Gbps for AES, 1.652 Mbps for RSA, 125.9/157.65 Mbps for HMAC-SHA1/MD5, and 2.56 Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability.

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Abstract: Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

Abstract: As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during automatic test pattern generation (ATPG), it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. It is often difficult and time consuming to identify these paths manually. This paper describes how to use diagnosis techniques to automatically identify these paths. Using this approach, the authors found most of these paths were false or multicycle paths inside DFT logic. These could be fixed by enhancing the timing exception paths used during ATPG to mask out transition values through these paths. Elimination of these paths resulted in a 300 MHz increase in the speed of the transition fault test pattern. However, occasionally the authors did find some failing paths were real functional problems and design changes were needed to resolve them

Design for Testability of Software-Based Self-Test for Processors

Abstract: In this paper, the authors propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design, and it enables at-speed testing and does not induce delay overhead

A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

Abstract: Testing mixed-signal circuits remains one of the most difficult challenges within the semiconductor industry. In this article, the authors present a novel DFT technique to test sets of ADCs and DACs embedded in a complex SiP. The technique provides fully digital testing on the converters to significantly reduce the cost of testing