Showing papers on "Design for testing published in 2008"

Power-Aware Testing and Test Strategies for Low Power Devices

Abstract: Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices

Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures

Abstract: Scan chain based attacks are a kind of side channel attack, which targets one of the most important feature of today's hardware - the test circuitry. Design for Testability (DFT) is a design technique that adds certain testability features to a hardware design. On the other hand, this very feature opens up a side channel for cryptanalysis, rendering crypto-devices vulnerable to scan-based attack. Our work studies scan attack as a general threat to stream ciphers and arrives at a general relation between the design of stream ciphers and their vulnerability to scan attack. Finally, we propose a scheme which we show to thwart the attacks and is more secure than other contemporary strategies.

Low Power Scan Shift and Capture in the EDT Environment

Abstract: This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.

Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design

Abstract: The author proposes a novel testing-based watermarking scheme for intellectual-property (IP) identification in this paper. The principles are established for the development of new watermarking IP-identification procedures that depend on current IP-based design flow. The core concept is embedding a watermark-generating circuit (WGC) and a test circuit into the IP core at the behavior design level. Therefore, this scheme can also successfully survive synthesis, placement, and routing and can identify the IP core at various design levels. This method adopts current main system-on-a-chip (SOC) design-for-test (DFT) strategies. The identity of the IP is proven during the general test process without implementing any extra extraction flow. After the chip has been manufactured and packaged, it is still easy to detect the identification of the IP provider without the need to examine the microphotograph. On real designs, our approaches entail low hardware overhead, tracking costs, and processing-time costs. The proposed method solves the IP-identification problem.

An Introduction to Logic Circuit Testing

Abstract: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

Abstract: This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors.

Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs

Abstract: We propose a testing methodology for analog and radio-frequency (RF) circuitry that incorporates digital circuits for performance calibration and adaptation. We explore the reuse of built-in digital calibration circuitry, along with minor digital design-for-testability (DfT) modifications, to test and characterize analog/RF circuit performance. By observing the digital tuning signals captured in the digital calibration circuitry, the analog/RF performance can be closely estimated, thus enabling cost-effective Go/No-Go production testing. In this paper, we illustrate this testing methodology using a case study of a digitally-calibrated Weaver image-reject receiver.

External Loopback Testing Experiences with High Speed Serial Interfaces

Abstract: Data eye margin test used in conjunction with loopback configuration has become a popular design for test (DFT) based test method for high speed links. This paper summarizes the DFT circuitry and test methods for supporting high speed serial interfaces (e.g. S-ATA,). The challenges of no-touch test methods in an external loopback environment are discussed. We close with a summary of our manufacturing experiences and directions for future improvement.

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Abstract: This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

Scan chain clustering for test power reduction

Abstract: An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.

Test Power Reduction by Blocking Scan Cell Outputs

Abstract: Power consumption during scan-based test becomes a major concern in modern nanometer technologies. Gating the outputs of scan cells can dramatically reduce the scan shift power. In this paper, we utilize the same gating logic at the outputs of scan cells to reduce the capture power consumption. This is achieved by inserting block enable cells (BECs) into the design to dynamically control the gating logic. During capture the BECs enable the gating logic to block the transitions originated from a subset of scan chains or scan segments propagating to combinational logic in order to reduce capture power. The implementation of the proposed method in test compression environment is also discussed. The experimental results on industrial designs show the significant capture power reduction by using proposed techniques.

Intellectual property authentication by watermarking scan chain in design-for-testability flow

Abstract: This paper proposes an intellectual property (IP) protection scheme at the design-for-testability (DfT) stage of VLSI design flow. Additional constraints generated by the owner's digital signature have been imposed on the NP-hard problem of ordering the scan cells to achieve a watermarked solution which minimizes the penalty on power and cost of testing. As only the order of the scan cells is varied, the number of test vectors for the desired fault coverage is not affected. The advantage of this scheme is the ownership legitimacy can be publicly authenticated on-site by IP buyers after the chip has been packaged by loading a specific verification code into the scan chain. We propose to integrate the scan chain watermarking with dynamic watermarking of the IP core to make the design hard-to-attack while the ownership is easy-to- trace. The proposed scheme is applied to an optimization instance of scan cell ordering targeting at test power reduction. The results on several MCNC benchmarks show that the watermarking scheme has a very low probability of solution coincidence and hence provides strong proof of authorship.

Digital design and fabrication

Abstract: Fabrication and Technology. Memory and Storage. Design Techniques. Design for Low Power. Testing and Design for Testability.

A Study on Design for Testability in Component-Based Embedded Software

Abstract: Effective implementation of test automation requires taking testing into account in the system design. In short, this is called design for testability (DFT). In this paper a study on DFT in component-based embedded software is presented, based on the interviews and technical documentation from two large-scale companies in the European telecom industry. The way test automation is addressed and the different techniques applied to make this more effective at the architectural level are described. The differences and benefits of different approaches are discussed.

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

Abstract: This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns

Abstract: This paper presents a scan-based DFT technique that uses limited number of enhanced scan cells to reduce volume of delay test patterns and improve delay fault coverage. The proposed method controls a small number of enhanced scan cells by the skewed-load approach and the rest of scan cells by the broadside approach. Inserting enhanced scan cells reduces test data volume and ATPG run time and improves delay fault coverage. Hardware overhead for the proposed method is very low. The scan inputs where enhanced scan cells are inserted are selected by gain functions, which consist of controllability costs and usefulness measures. A regular ATPG can be used to generate transition delay test patterns for the proposed method. Experimental results show that test data volume is reduced by up to 65% and fault coverage is improved by up to about 6%.

Power Analysis and Reduction Techniques for Transition Fault Testing

Abstract: This paper examines the differences in power consumption characteristics of two popular ATPG techniques for transition fault testing (TFT) -- launch off shift (LOS) and launch off capture (LOC). These differences have critical implications on the circuit switching during the launch and capture cycles, and if unaddressed, can lead to IR drop issues and unwarranted silicon failures. Our investigations show that power consumption in the launch cycle for LOS patterns can be as high as 1.96 times the corresponding number for LOC patterns. We systematically understand the reasons for this difference and propose a variety of power-aware design-for-test (DFT) and automatic test pattern generation (ATPG) techniques to limit this power differential as well as general TFT power consumption. The proposed techniques include use of (a) fill techniques, (b) intelligent test and functional enable control of clock gates, and (c) pattern re-generation using low compression and low effort ATPG. Our experiments demonstrate the efficacy of the proposed techniques in reducing power consumption, and the associated trade-offs in pattern volume.

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

Abstract: This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor test structures are reviewed and corresponding models discussed.

The Test Features of the Quad-Core AMD Opteron- Microprocessor

Abstract: This paper describes the design-for-test (DFT) features of the quad-core AMD-OpteronTM microprocessor.

Verification and Analysis of Self-Checking Properties through ATPG

Abstract: Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect and compensate errors online. However, during synthesis and optimization self-checking properties can be destroyed. This paper shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. As a result the properties are either verified or the fault detection profile provided by ATPG can be used to increase the error detection or fault tolerance capabilities of the design. Experimental data are shown for several self-checking arithmetic circuits.

Design-for-testability techniques for motion estimation computing arrays

Abstract: In this paper, a testable 2-D motion estimation (TME) design at the bit level (TMEbit) based on the C-testability conditions are proposed. In order to meet the testability conditions, the bit-level cell functions are made bijective. Our C-testability conditions guarantee about 100% fault coverage for single cell fault model with a constant number of test patterns. The number of test patterns is 128. To verify the proposed technique, an experimental chip is implemented with TSMC 0.18 mum technology. According to experimental results, the gate count of the design is about 159 K and the design can operate at the frequency up to 100 MHz. The hardware overhead used to make it C-testable is about 7%.

Evaluation of Entropy Driven Compression Bounds on Industrial Designs

Abstract: The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution space for compression based designs and discusses the various parameters which result in test tradeoffs. The discussion is supported with elaborate experimental data. Through them, the paper offers an insight into the solution space of compression techniques and makes resulting recommendations.

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

Abstract: Asynchronous design offers an attractive solution to overcome the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market due to a lack of testing methodology and support. This paper first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

A Scan-Based Delay Test Method for Reduction of Overtesting

Abstract: This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.

Design for assembly

Abstract: Purpose – The purpose of this paper is to explain the growing importance of design for assembly (DFA) and design for test (DFT) for compact medical electronics products.Design/methodology/approach – The paper discusses compact products based on leading‐edge electronic components such as digital signal processors, radio frequency (RF) and mixed‐signal chips, advanced ball‐grid array, quad flat pack, chip scale package devices.Findings – Advanced technologies like these create higher component and joint counts and increasing PCB densities. A higher probability of defects and faults is created, which lead to lower yields for a specific product line unless proper effective DFA and DFT are implemented.Practical implications – The paper details DFA, high‐speed PCB design, mixed‐signal design, and DFT.Originality/value – With increasing complexity in compact medical products, it is prudent to emphasize DFA and DFT for ultimate reliability during product development and production cycles.

Scan chain organization for embedded diagnosis

Abstract: Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.

Low Power Test for Nanometer System-on-Chips (SoCs)

Abstract: Shrinking power consumption budgets and increasing use of low power design techniques in nanometer designs are forcing test engineers to examine the two problems of (a) reducing power consumption in the test mode of circuit operation, and (b) testing the device in the presence of various power management structures. This paper examines the various concerns associated with this domain (often referred to as low-power or power-aware test), identifies the relevant design and test challenges, surveys salient solutions along with the associated trade-offs, and identifies open topics that require further attention from researchers in both academia and industry.

HDL Design Structure for Integrating Test Structures into an Integrated Circuit Design

Abstract: A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.

Low-Cost Scan Test for IEEE-1500-Based SoC

Abstract: In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.