Showing papers on "Design for testing published in 2010"

A structured and scalable test access architecture for TSV-based 3D stacked ICs

Abstract: New process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a DfT test access architecture for such 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The DfT architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. It adds a die-level wrapper, which is based on IEEE 1500, with the following novel features: (1) dedicated probe pads on the non-bottom dies to facilitate pre-bond die testing, (2) TestElevators that transport test control and data signals up and down during post-bond stack testing, and (3) a hierarchical Wrapper Instruction Register (WIR) chain. The paper also hints at opportunities for optimization and standardization of this architecture.

Testing TSV-based three-dimensional stacked ICs

Abstract: To meet customer's product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing 3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.

3D DfT architecture for pre-bond and post-bond testing

Abstract: Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as post-bond stack testing of both partial and complete stacks. The architecture enables on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow flexible optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1500 or IEEE Std 1149.1. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

Production test challenges for highly integrated mobile phone SOCs — A case study

Abstract: Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded FM radio, and a complete RF transceiver for mobile communication. The paper describes the production test approaches for different groups of embedded circuitry, e.g. digital logic, mixed-signal, etc. Design-for-Test measures are briefly described. A breakdown of relative test times, proportional to production test cost, with respect to different groups of circuitry is presented. Limitations of existing test equipment and future challenges in order to further reduce test cost for complex SOCs are explained based on industrial implementation experience.

Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access

Abstract: Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.

Secure and testable scan design using extended de Bruijn graphs

Abstract: In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced.

Multidimensional Fitness Function DPSO Algorithm for Analog Test Point Selection

Abstract: A novel multidimensional fitness function discrete particle swarm optimization algorithm is proposed to optimize analog test point selection. The proposed method uses fault isolation rate and the number of test points to formulate a multidimensional fitness function to search the global minimal test point set, and an elitist set is used to get more than one possible best solution in the described approach. The efficiency of the proposed method is proven by the same experiments used to verify other methods for optimal test points. Results show that the proposed algorithm in this paper cannot only reduce the computation complexity but also shorten the time consumption. It is particularly useful for large-scale analog circuits.

Test, validation, and debug architecture

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Fault Tolerant QCA Logic Design With Coupled Majority-Minority Gate

Abstract: Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA logic. In the current work, we investigate cost effective DFT for QCA designs realized with CMVMIN. The fault effects at the gate outputs due to cell deposition and cell misplacement defects are characterized for concurrent testable circuit design. The effective use of unutilized outputs of CMVMIN gates, realizing a circuit, leads to the proposed fault tolerant design that may not be possible with the conventional gate structures.

Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property

Abstract: Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design, and is vulnerable to removal attack as the test logic is independent of the functional logic. In this paper, we propose a publicly detectable watermarking scheme to bridge the gap between IP protection and IP management. The design is watermarked by means of synthesis-for-testability (SfT), where the test and functional logics of the IP are merged and synthesized together without using scannable flip-flops. Watermarked constraints are imposed on the scan chain ordering problem in the SfT process so that ownership of the embedded IP can be publicly identified by lawful IP providers, buyers and consumers by injecting a specific test vector in the field. The overhead due to the watermark insertion is minimized by a nearest neighbor search algorithm for flip-flop reordering. As the scan function is an integral part of the design in the synthesis process of the IP creation, the watermark is harder to be removed relative to other scan chain watermarking schemes whose test circuits are logically independent of the IP functionality. To deter and track IP fraudulence by the licensees, a provable mechanism is proposed to enable multiple authorships of different IP cores in a single chip to be publicly authenticated in the field. Experiments performed with ISCAS89 and LGSyn93 benchmark circuits show that the proposed watermarked designs have low design overheads, and the probabilities of coincidence and removal reduce rapidly with increased watermark and scan chain length.

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging

Abstract: Scan is a known design-for-test technique in manufacturing test that has been successfully applied also to aid post-silicon debugging on testers. However, to achieve real-time observability in-field, embedded trace buffers are needed. In this paper, we discuss how in the presence of enhanced scan chains, trace buffers can be utilized efficiently for real-time debug data acquisition in-field.

SOC Test Architecture and Method for 3-D ICs

Abstract: 3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.

Complex Oscillation-Based Test and Its Application to Analog Filters

Abstract: Testing is a critical factor for modern large-scale mixed-mode circuits. Strategies for mitigating test cost and duration include moving significant parts of the test hardware on-chip. This paper presents a novel low-overhead approach for design for test and built-in self-test of analog and mixed-mode blocks, derived from the oscillation-based test framework. The latter is enhanced by the use of complex oscillation regimes, improving fault coverage and enabling forms of parametric or specification-based testing. This technique, initially proposed targeting large subsystems such as A/D converters, is here illustrated at a much finer granularity, considering its application to analog-filter stages, and also proving its suitability to backfit existing designs. The simple case of a switched-capacitor second-order bandpass stage is used for illustration discussing how deviations from nominal gain, central frequency, and quality factor can be detected from measurements not requiring A/D stages. A sample design is validated by simulations run at the layout level, including Monte Carlo analysis and simulations based on random fault injections.

DFTT: Design for Trojan Test

Abstract: Due to the globalization of the Integrated Circuit (IC) manufacturing industry, hardware Trojans constitute an increasingly probable threat to both commercial and military applications. As traditional testing methods fall short in finding hardware Trojans, several specialized detection methods have surfaced. To facilitate research in this area and embed internal barriers to prevent Trojan attacks both at the design level and at the manufacturing level, we propose a Design-for-Trojan-Test (DFTT) methodology. DFTT is based on one key principle: increase the complexity for hardware Trojan attackers, thereby making successful hardware Trojan-based attacks extremely difficult to accomplish. A DFTT tool is also developed to automate the hardening process. The effectiveness of our Trojan prevention method is demonstrated on the Trivium encryption core.

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

Abstract: Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X -filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.

On signal tracing in post-silicon validation

Abstract: It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow. Tracing internal signals during circuit's normal operation, being able to provide real-time visibility to the circuit under debug (CUD), is one of the most effective silicon debug techniques and has gained wide acceptance in industrial designs. Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers. In this paper, we provide in-depth discussion for trace-based debug strategy and review recent advancements in this important area.

Advanced modeling of faults in Reversible circuits

Abstract: This survey provides an overview of some recent developments in the testing and design validation of reversible logic circuits Reversible circuits are of interest in ultra-low-power design and in quantum information processing. We describe the fault and error models that have been proposed for these circuits and summarize their properties. We also discuss algorithms for automatic test pattern generation, design-for-testability techniques, and design debugging. We conclude by briefly examining the relationship between classical reversible circuits and quantum circuits.

Low-capture-power at-speed testing using partial launch-on-capture test scheme

Abstract: Most previous DFT-based techniques for low-capture-power broadside testing can only reduce test power in one of the two capture cycles, launch cycle and capture cycle. Even if some methods can reduce both of them, they may make some testable faults in standard broadside testing untestable. In this paper, a new test application scheme called partial launch-on-capture (PLOC) is proposed to solve the two problems. It allows only a part of scan flip-flops to be active in the launch cycle and capture cycle. In order to guarantee that all testable faults in the standard broadside testing can be detected in the new test scheme, extra efforts are required to check the overlapping part. In addition, calculation of the overlapping part is different from previous techniques for the stuck-at fault testing because broadside testing requires two consecutive capture cycles. Therefore, a new scan flip-flop partition algorithm is proposed to minimize the overlapping part. Sufficient experimental results are presented to demonstrate the efficiency of the proposed method.

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers

Abstract: This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented.

Test Time Analysis for IEEE P1687

Abstract: The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

Recent Advances in Analog, Mixed-Signal, and RF Testing

Abstract: Due to the lack of widely applicable fault models, testing for analog, mixed-signal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

DfT optimization for pre-bond testing of 3D-SICs containing TSVs

Abstract: This paper proposes to provide testability for the breaking point produced by the Through-Silicon-Vias (TSVs) of 3D-Stacked ICs (3D-SICs) during pre-bond testing with low Design-for-Testability (DfT) cost. Different from prior solutions which utilize two additional wrapper cells for the breaking point at each TSV, this paper proposes to provide the testability of two ends of the TSVs respectively by reusing the existing Primary-Inputs (PIs)/ Primary-Outputs (POs) and Pseudo-PIs/Pseudo- POs (PPIs/PPOs). To further reduce the hardware overhead and enhance the efficiency of the proposed method, this paper has also proposed the metrics and algorithm on deciding the selecting order of the TSVs and the PIs/PPIs (POs/PPOs) to be reused. The experimental results on larger ITC'99 benchmark circuits validate the effectiveness of the proposed method.

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

Abstract: This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

A Fully Integrated Built-In Self-Test $\Sigma{-}\Delta$ ADC Based on the Modified Controlled Sine-Wave Fitting Procedure

Abstract: This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Σ-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.

A generic low power scan chain wrapper for designs using scan compression

Abstract: Shrinking power budgets in low power system-on-chips (SoCs) have elevated test power consumption as a major consideration for chip design and test engineering teams. Many traditional automatic test pattern generation (ATPG) and design-for-test (DFT) techniques for test power reduction are either effective for circuits not using test data compression hardware or have implications on the physical design cycle. This paper describes a technique for reducing peak current during scan based testing that can work in the presence of compression, and impose no restrictions on physical design, e.g. related to chip clocking. We propose low-design effort modifications to the test compression logic (wrapper-like changes) that enable us to (a) bypass scan chains or groups of them and (b) shift in constant values into the bypassed flip-flops for lowering the instantaneous current drawn. The modifications are easily localized to a scan chain wrapper that can be used with any scan compression solution. An SoC using lowpower scan chain wrappers provides sufficient configurability (scan chains bypassed or scan chains included) to explore different power reductions with test cost trade-offs. We describe a methodology that allows us to manage the inherent configurability available in our solution. For empirical validation, we have implemented low-power scan chain wrappers for a subset of scan chains in a recently taped-out 65nm low-power SoC. We present experimental data from ATPG and initial silicon power measurements for this chip to demonstrate the benefits and limitations of the proposal.

Design of a Realistic Test Simulator For a Built-In Self Test Environment

Abstract: This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) proce- dure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational pur- poses for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs.

Special session 6C: New topic mixed-signal test impact to SoC commercialization

Abstract: With the growing presence of analog and mixed-signal blocks in SoC designs, test and validation cost and quality of mixed-signal circuits is taking the spotlight within the semiconductor industry. This is compounded by the fact that recent innovations in digital test have dramatically reduced the cost of testing digital blocks while analog and mixed-signal blocks are still being tested using brute force methods resulting in a growing contribution of analog test cost to the overall SoC test cost. As a result test cost of mixed-signal blocks in an SoC is becoming an inhibiting factor in commercializing cost effective mixed-signal SoCs. The issue is most pronounced in SoCs with power management and RF components. The normalized cost of test per mm2 of mixed-signal blocks is at least 10 higher than digital blocks. It is therefore imperative for the industry to rapidly advance analog test and characterization to the same level of efficiency as digital in order to effectively manage the test cost and quality of mixed signal SoCs. One of the primary problems is that two of the fundamental building blocks of a test strategy are missing: there is nothing equivalent to automatic test-pattern generation for analog, and that is mainly because there is no practical fault model for analog circuits and DFT and BIST are being used for analog circuits but they are custom efforts for each circuit. The lack of a practical fault model is making it impossible to truncate test effeort while guranteeing test quality before silicon production is fully ramped. In this paper, we will discuss major contributing factors to this trend and examine potential solutions to address the issue. Karim Arabi's bio: Karim Arabi is Sr. Director, Engineering at Qualcomm where he is responsible for leading DFT and EDA across the company. He held key technical management positions at PMC Sierra and Cirrus Logic. Karim was a founder of Opmaxx, Inc., an innovative startup in analog design and test automation, acquired by Credence. Karim's main research interest includes DFT, BIST, low power design, design methodology development and design automation. Karim received his Ph.D. and M.Sc. degrees in Electrical Engineering from Ecole Polytechnique of Montreal and his B.Sc. degree in Elctronics from Tehran Polytechnic.

A Unified Approach for IP Protection across Design Phases in a Packaged Chip

Abstract: IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode. The signature of the owner of physical design tool along with that of logic design tool can separately be embedded while designing the scan tree and also verified from the packaged chip without conflict using two distinct modes. A bi-objective minimization of overhead in routing and power is supported through our scheme. Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage

Abstract: Functional test sequences play an important role in manufacturing test for targeting defects that are not detected by structural test. In practice, functional tests are often derived from existing design-verification test sequences and they suffer from low defect coverage. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a non-scan DFT technique at the register-transfer (RT) level that tackles the above problem in three steps. It can be used to increase the defect coverage for scan-based designs by making functional test sequences more effective in native (non-scan) mode. The proposed method selects a small set of control points, and through an efficient branch-and-bound strategy, determines an effective set of truth assignments to these control points (also called test modes). The original functional test is expanded by applying the same functional test sequence once with each selected test mode. Finally, a small set of state elements are chosen as observation points from the transitive fanout cone of the control points based on the number of recorded transitions. The proposed DFT method is evaluated in terms of the unmodeled defect coverage, and we introduce a new surrogate metric, called multi-segment long path sensitization, for the purpose of evaluation. Experimental results for the ITC'99 benchmark circuits, the Open RISC 1200 SoC benchmark, and the Scheduler module of the Illinois Verilog Model (IVM) show that the proposed non-scan DFT technique offers significant potential for ramping up the defect coverage of existing functional test sequences.