Showing papers on "Design for testing published in 2012"

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Abstract: This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.

Are advanced DfT structures sufficient for preventing scan-attacks?

Abstract: Standard Design for Testability (DfT) structures are well known as potential sources of confidential information leakage. Scan-based attacks have been reported in publications since the early 2000s. It has been shown for instance that the secret key for symmetric encryption standards (DES, AES) could be retrieved from information gathered on scan-out pins when scan-chains are fully observed through these pins. However DfT practices have progressed to adapt to large and complex designs such as test response compaction, associated X-masking structure, partial scan, etc. As a side effect, these techniques mask part of the information collected on scan outputs. Thus, at first glance, they may appear as countermeasures against scan-based attacks. Nevertheless, in this paper we show that DfT structures, regardless of their nature, do not inherently enhance security and that specific additional countermeasures are still needed. We propose a new-scan attack able to deal with designs where only part of the internal circuit's state is observed for test purpose.

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

Abstract: 3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance.

Test access architecture for TSV-based 3D stacked ICS

Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Abstract: Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

Dynamically changeable secure scan architecture against scan-based side channel attack

Abstract: Scan test which is one of the useful design for testability techniques is effective for LSIs including cryptographic circuit. It can observe and control the internal states of the circuit under test by using scan chain. However, scan chain presents a significant security risk of information leakage for scan-based attacks which retrieves secret keys of cryptographic LSIs. In this paper, a secure scan architecture against scan-based attack which still has high testability is proposed. In our method, scan data is dynamically changed by adding the latch to any FFs in the scan chain. We show that by using proposed method, neither the secret key nor the testability of an RSA circuit implementation is compromised, and the effectiveness of the proposed method.

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Abstract: Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

Abstract: This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chip's ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

A New Scan Attack on RSA in Presence of Industrial Countermeasures

Abstract: This paper proposes a new scan-based side-channel attack on RSA public-key cryptographic implementations in the presence of advanced Design for Testability (DfT) techniques. The attack is performed on an actual hardware implementation, for which different test scenarios were conceived (response compaction, X-Masking). The practical aspects of scan-based attacks on the RSA cryptosystem are also presented. Additionally, a novel scan-attack security analysis tool is proposed which helps in evaluating the scan-chain leakage resilience of security circuits.

A new scan attack on RSA in presence of industrial countermeasures

Abstract: This paper proposes a new scan-based side-channel attack on RSA public-key cryptographic implementations in the presence of advanced Design for Testability (DfT) techniques. The attack is performed on an actual hardware implementation, for which different test scenarios were conceived (response compaction, X-Masking). The practical aspects of scan-based attacks on the RSA cryptosystem are also presented. Additionally, a novel scan-attack security analysis tool is proposed which helps in evaluating the scan-chain leakage resilience of security circuits.

A Scan-Based Side Channel Attack on the NTRUEncrypt Cryptosystem

Abstract: Scan-based Design-for-Test (DFT) is a widely deployed technique for testing hardware chips. Using this approach, all flip-flops in the design under test are connected to a scan chain where their states can be scanned out through this chain during the testing phase. Scan-based side channel attacks exploit the information obtained by analyzing the scanned data in order to retrieve secretinformation from cryptographic hardware devices that are designed with this testability feature. The NTRU encryption algorithm (NTRUEncrypt) is a parameterized family of lattice-based public key cryptosystems which has recently been accepted to the IEEE P1363 standards under the specifications for lattice-based public-key cryptography. In this paper, we present a scan-based side channel attack on NTRUEncrypthardware implementations that employ scan based DFT techniques. Our attack determines the scan chain structure of the polynomial multiplication circuits used in the decryption algorithm which allows the cryptanalyst to efficiently retrieve the secret key.

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures

Abstract: This paper presents a scan-based attack on hardware implementations of Elliptic Curve Cryptosystems (ECC). Several up-to-date Design-for-Testability (DfT) features are considered, including response compaction, X-Masking and partial scan. Practical aspects of the proposed scan-based attack are described, namely timing and leakage analysis that allows finding out data related to the secret key among the bits observed through the DfT structures. We use an experimental setup which allows full automation of the proposed scan attack on designs including DfT configurations. We require around 8 chosen points to implement the attack for retrieving a 192-bit scalar.

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing

Abstract: 3D integration is a promising technology that provides high memory bandwidth, reduced power, shortened latency, and smaller form factor. Among many issues in 3D IC design and production, testing remains one of the major challenges. This paper introduces a new design-for-test technique called 3D-GESP, an efficient Built-In-Self-Repair (BISR) algorithm to fulfill the test and reliability needs for 3D-stacked memories. Instead of the local testing and redundancy allocation method as most current BISR techniques employed, we introduce a global 3D BISR scheme, which not only enables redundancy sharing, but also parallelizes the BISR procedure among all the stacked layers of a 3D memory. Our simulation results show that our proposed technique will significantly increase the memory repair rate and reduce the test time.

Eliminating Performance Penalty of Scan

Abstract: Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

Abstract: The paper presents novel testability analysis method applicable to register-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

An Easily Testable Routing Architecture and Prototype Chip

Abstract: Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Abstract: Scan test is one of the useful design for testability techniques, which can detect circuit failure efficiently. However, it has been reported that it's possible to retrieve secret keys from cryptographic LSIs through scan chains. Therefore testability and security contradicted to each other, and there is a need to an efficient design for testability circuit so as to satisfy both testability and security requirement. In this paper, a secure scan architecture against scan-based attack is proposed to achieve high security without compromising the testability. In our method, scan structure is dynamically changed by adding the latch to any FFs in the scan chain. We made an analysis on an RSA circuit implementation to show the effectiveness of the proposed method and discussed how our approach is resistant to scan-based attack.

Low power scan by partitioning and scan hold

Abstract: Scan testing dynamic power consumption can induce reliability problems in the circuit under test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning technique, supported by a scan hold mechanism, for low power dissipation during the shift phase of the scan testing procedures. Substantial power reductions can be achieved either in built-in self test (BIST) or non-BIST scan-based testing environments, without test application time increase, fault coverage decrease, scan cell reordering and clock gating.

New Design for Testability Approach for Clock Fault Testing

Abstract: We propose a new design for testability approach for testing clock faults of next generation high performance microprocessors. In fact, it has been shown that conventional manufacturing test is unable to guarantee their detection, although they could compromise the effectiveness of delay fault testing, as well as the microprocessor correct operation in the field. These conditions will of course worsen with technology scaling, due to the expected increase in fault likelihood, included clock faults. To deal with these problems we propose a design for testability approach that, by means of simple modifications to conventional clock buffers, allows clock fault detection through any conventional manufacturing test approach. This is achieved at the cost of very low increase in area and power consumption of clock buffers, and with no additional test cost or impact on the microprocessor performance and in-field operation. We then introduce a possible further modification to clock buffers that, at additional limited costs in terms of area and power consumption, allows their calibration after fabrication in order to compensate for parameter variations possibly occurring during manufacturing, thus minimizing the likelihood of either false test fails, or test misses. As an example, we show the application of our approach to the clock distribution network of the Pentium® 4 microprocessor (Other names and brands may be claimed as property of others). However, it can be applied to the clock distribution of any high performance ASIC, or microprocessor.

A DFT methodology targeting online testing of reversible circuit

Abstract: Reversible logic is gaining importance for its ultra low power consumption. It has wide application in quantum computing, nanotechnology and optical computing. In this work, we propose a DFT (design for test) methodology for reversible logic blocks to enable online fault detection. A concurrent error detection technique, based on parity is introduced for the online testing. The methodology proposed for converting a 3×3 reversible gate into an online testable circuit ensures detection of all the stuck-at faults, bit flip faults and almost all multiple bit faults in logic blocks.

Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

Abstract: This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the pattern. After filling the X-bits for shift power reduction, the patterns are compressed based on shifted alternating frequency directed run-length coding, which is suitable for encoding pre-computed test set of embedded cores in System-on-Chip(SoC). The experimental results on ISCAS'89 benchmark circuits show that our scheme provides better compression efficiency as well as significant reduction in test power.

Scan-Based Speed-Path Debug for a Microprocessor

Abstract: Identifying the actual speed limiting paths in silicon using traditional functional microprocessor tests can be very time-consuming and expensive because of limited observability of internal signals. This paper presents the development of a promising scan-based speed path diagnosis methodology and illustrates its application to a high performance microprocessor design.

Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

Abstract: This paper presents modified version of a realistic test tool suitable to Design For Testability (DFT) and Built-In Self Test (BIST) environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test (CUT). The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer (PC) platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface (GUI) procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems

Abstract: Precisely measuring specifications of differential analog and mixed-signal circuits is a difficult problem for self-test development because the imbalance introduced by the design-for-test circuitry on the differential signaling causes nonlinearity on the test stimulus, resulting in degrading device-under-test (DUT) performance. This problem triggers low test accuracy and serious yield loss. This brief proposes a novel test methodology to accurately predict individual DUT specifications by overcoming the imbalance problem with the imbalance generator, a radio-frequency transformer, and a programmable capacitor array based on a loopback test configuration. The imbalance generator produces spectral loopback responses of different weight. Nonlinear equations are then derived to characterize DUT specifications. Hardware measurement results show that this approach can be used to predict the specifications of a DUT in a production test.

The testability modeling and model conversion technology based on multi-signal flow graph

Abstract: Along with the increase of the level of complexity, integration and intelligence of system, prognostics and health management technology (PHM) has gotten more and more attention and application. The technology has become the key technology of increasing the reliability, testability, maintainability, supportability and safety of complex system. Doubtless the higher requirements are put forward to the testability technology. The testability modeling and model conversion technology are more and more emphasized by the product designer with widespread application for design for testability. In this paper, the testability modeling and model conversion technology based on the multi-signal flow graph are introduced. After describing the basic principle of testability model, the paper discussed the method of testability modeling and analysis and the method of model conversion. Finally, by using a PDU controller of momentum drive equipment of some airplane, it is validated that the methods are valid. At the same time, results show that the methods are feasible and effective in the design for PHM of modernized equipment.

An innovative approach of computational fault detection using design for testability of CP-PLL

Abstract: This paper presents an innovative approach to detect computational fault using design for testability (DFT) of CP-PLL (charge pump phase locked loop) to allow simple digital testing. The proposed structure is useful in mixed signal IC (incorporating both analog and digital block on the same chip) testing. With increasing complexity of mixed signal IC the demand of preparing the low cost testing circuitry also gets increased. Here CP-PLL is taken as the mixed signal IC wherein the proposed method uses the charge pump as stimulus generator and the VCO (voltage controlled oscillator) as measuring device for testing the CP-PLL. It avoids the need of interfacing any foreign component and decreases the area overhead of whole IC. Moreover, testing circuitry is applied at the digital part of the CP-PLL i.e. PFD (phase frequency detector) and the analog part i.e. charge pump; loop filter and VCO are controlled by PFD only. Consequently the efficiency of the testing process avoiding the loading effect at analog node is increased. Fault simulation results indicate that the proposed structure posses high fault coverage of 98.2% and less area overhead of about 3.025%.

Test challenges in designing complex 3D chips: what is on the horizon for EDA industry?

Abstract: Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form a system. Compared to conventional wire-bond chip interconnections, TSVs offer several advantages such as high density, low latency, low power, and possibly lower cost. TSVs provide vertical interconnects and hence naturally used for 3D vertical stacking of multiple dies, However, TSVs also have attractive benefits in interconnecting dies, which are placed next to each other on top of a passive silicon interposer.TSMC has proposed CoWoS (Chip-on-Wafer-on-Substrate) process as the standard design paradigm to assemble interposer-based 3D ICs. Figure 1 shows an example of a CoWoS design with three heterogeneous (RF, logic and memory) dies. In order to reach quality requirements for volume production, several challenges need to be resolved for 3D ICs. Many of these challenges open up new horizon for the EDA industry and academia as they require innovative and compute efficient approaches.One of the critical challenges is effective and efficient testing of 3D ICs. Just like traditional 2D chips, 3D chips need to be tested for possible manufacturing defects. To minimize any yield loss and reduce overall cost, each die should not only be fully tested before stacking, but also post-stacking re-testing of individual dies is required to confirm that the stacking process did not damage the individual die. In addition, a new kind of test must be performed to check that inter-die interconnects are defects free. Furthermore, the passive silicon interposer needs to be tested in order to not become the bottleneck and the major yield killer in the overall design process. In this paper, we describe some of the innovative solutions developed by TSMC in this direction. The paper highlights complexities and issues related to test architecture development and automation, test flow optimization as well as testing of passive interposer that requires special focus from the EDA industry.

Roadmap for design and EDA infrastructure for 3D products

Abstract: This article consists of a collection of slides from the author's conference presentation on the design and electronic design automation (EDA) infrastructure for three-dimensional mobile display products. Some of the specific topics discussed include: EDA design methodologies; options for chip design; memory capacity; evolving 3D technologies; ecosystems for 3D designs; thermal challenges; inventories of core design technologies; design environments for interposers; and the design environment for logic on logic design.