Showing papers on "Design for testing published in 2014"

Semiconductor Memories Technology, Testing And Reliability

Abstract: Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including.* Memory cell structures and fabrication technologies.* Application-specific memories and architectures.* Memory design, fault modeling and test algorithms, limitations, and trade-offs.* Space environment, radiation hardening process and design techniques, and radiation testing.* Memory stacks and multichip modules for gigabyte storage.

Radiated Two-Stage Method for LTE MIMO User Equipment Performance Evaluation

Abstract: Two-stage method for long-term-evolution (LTE) multiple-input-multiple-output (MIMO) wireless user equipment (UE) performance evaluation is one of the methods proposed for standard organizations. However, the conducted two-stage method has been challenged for its lack of support for “over-the-air” (OTA) as well as for its negligence of the self-interference in the device under test (DUT) in the throughput test. Self-interference in DUT such as cell phones could significantly reduce receiver sensitivity, thus, if not properly included in the test setup, could affect the test accuracy. In order to solve the problems, a radiated two-stage (RTS) test method for LTE MIMO UE test is presented in this paper. By applying an invert calibration matrix to the input signal of the throughput test, the proposed method performs OTA second-stage test, which eliminates the problems of connecting an RF cable directly to the DUT receiver. The RTS OTA MIMO test method can be executed in a standard single-input-single-output anechoic chamber, reduces overall system cost, and offers high reliability and repeatability. Meanwhile, the measurement provides extensive subcomponent-level performance information and makes it an ideal solution for both research and development (R&D) and certification test.

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Abstract: Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.

CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition

Abstract: The fourth edition of CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art technology issues highlighted by the widespread use of nanometer-scale CMOS technologies In this latest edition, virtually all chapters have been re-written, the transistor model equations and device parameters have been revised to reflect the sigificant changes that must be taken into account for new technology generations, and the material has been reinforced with up-to-date examples The broad-ranging coverage of this textbook starts with the fundamentals of CMOS process technology, and continues with MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, arithmetic building blocks, clock and I/O circuits, low power design techniques, design for manufacturability and design for testability

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU

Abstract: Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels

Abstract: Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and reliability of 3-D stacked integrated circuits, hence these defects need to be screened early in the manufacturing flow. Before wafer thinning, TSVs are buried in silicon and cannot be mechanically contacted, which severely limits the test access. Although TSVs become exposed after wafer thinning, probing on them is difficult because of TSV dimensions and the risk of probe-induced damage. To circumvent these problems, we propose a non-invasive method for pre-bond TSV test that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their resistor-capacitor parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect the resistive open and leakage faults. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. We provide a method to create a regression model to predict the defect size for a given measured period period of the ring oscillator, and a method for accuracy analysis. Results on fault detection effectiveness are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The estimated design for testability area cost of our method is negligible for realistic dies.

Advanced Techniques for Designing Stealthy Hardware Trojans

Abstract: The necessity of detecting malicious modifications in hardware designs has led to the development of various detection tools. Trojan detection approaches aim to reveal compromised designs using several methods such as static code analysis, side-channel dynamic signal analysis, design for testing, verification, and monitoring architectures etc. This paper demonstrates new approaches for circumventing some of the latest Trojan detection techniques. We introduce and implement stealthy Trojans designs that do not violate the functional specifications of the corresponding original models. The designs chosen to demonstrate the effectiveness of our techniques correspond to encryption algorithms and a pseudo random number generator. The proposed Trojans are inserted into the original RTL, and decrease the overall security of the designs, minimizing detection probability by state-of-the-art static analysis tools.

Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison

Abstract: Hardware implementation of cryptographic algorithms is subject to various attacks. It has been previously demonstrated that scan chains introduced for hardware testability open a back door to potential attacks. Here, we propose a scan-protection scheme that provides testing facilities both at production time and over the course of the circuit's life. The underlying principles to scan-in both input vectors and expected responses and to compare expected and actual responses within the circuit. Compared to regular scan tests, this technique has no impact on the quality of the test or the model-based fault diagnosis. It entails negligible area overhead and avoids the use of an authentication test mechanism.

Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits

Abstract: Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits.

Test generation and design-for-testability for flow-based mVLSI microfluidic biochips

Abstract: Advances in flow-based microfluidic biochips offer tremendous potential for biochemical analyses and clinical diag-nostics. However, the adoption of flow-based biochips is hampered by defects that are especially common for chips fabricated using soft lithography techniques. Recently published work on fault detection in flow-based biochips is based on logic-circuit modeling of the microfluidic channels and control valves, followed by classical test generation for digital circuits. However, this approach is not applicable to realistic designs because the circuit model is generated manually and many real defects are mapped to undetectable faults in the logic-circuit model. We present a technique for automated and hierarchical generation of the logic-circuit model from the layout of a flow-based microfluidic chip. Moreover, based on the analysis of untestable faults in the logic-circuit model, we present a design-for-testability (DfT) technique that can achieve 100% fault coverage. Two microfluidic VLSI (mVLSI) chips, each containing over 1500 valves, are used to demonstrate the automated model generation and DfT solutions.

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

Abstract: At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

Abstract: Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

Test and Design-for-Testability Solutions for 3D Integrated Circuits

Abstract: Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.

Testability Measurement Framework: Design Phase Perspective

Abstract: 3 Abstract: Measuring testability early in the development life cycle considerably reduces the overall development cost, effort and rework. It is very expensive and error prone decision to correct the design to get better testability after the coding has started. This paper proposes a testability measurement framework for object oriented software concerning at design phase. This framework correlates the testability factor with object oriented design properties and also correlates design properties with object oriented design metrics. No such framework has been presented in the literature that accurately measure testability of object oriented software taking design phase into consideration. The proposed framework reduces the gap between object oriented design properties, metrics and testability. This framework measures effort in measuring testability of object oriented software early at design phase and makes it possible to produce reliable end product within time and budget.

Testing PUF-based secure key storage circuits

Abstract: Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The scheme targets high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The scheme reuses existing FE sub-blocks (for pattern generation and compression) to minimize the area overhead. The scheme is integrated in FE design and simulated; the results show that a SAF fault coverage of 95.1% can be realized with no more than 50k clock cycles at the cost of a negligible area overhead of only 2.2%. Higher fault coverage is possible to realize at extra cost.

Hierarchical Model-Based Approach to Testability Modeling and Analysis for PHM of Aerospace Systems

Abstract: A prognostics and health management (PHM) technique has been developed and applied to a variety of safety-critical aerospace systems. The PHM performance relies highly on test data, which conveys relevant system health information, and design for testability (DFT) developed concurrently with system design is thus of great importance to PHM performance. The testability model is the basis for testability analysis and design. To address the problems that traditional testability models did not include such as any quantitative testability information that could not describe fault-evolution test dependency, a novel model referred to as a quantified uncertainty hierarchical model is presented. In the model, fault-test dependency was described through quantified directed graph and fault attributes; test attributes and propagation attributes were assigned to nodes and directed edges in the form of probability, fuzziness, and uncertainty at the system level. And at component level, the physics of the failur...

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

Abstract: Design For Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the hard test accessibility (especially for upper dies) and to the high complexity where each die can embed hundreds of IPs. In this paper we propose a DFT architecture based on IEEE P1687 to enable the test of 3D stacked ICs. The proposed test architecture allows the test at all 3D fabrication levels: pre-, mid-, and postbond levels. We present a test pattern retargeting flow using IEEE P1687 languages ICL (Instrument Connectivity Language) and PDL (Procedural Description Language), which allows easy retargeting from 2D (die-level) to 3D (stack-level). Compared to IEEE 1149.1 based 3D test architecture, our proposed 3D test architecture is more flexible and enhances test concurrency without an additional area cost.

Determining a quality parameter for a verification environment

Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.

Breaking Integrated Circuit Device Security through Test Mode Silicon Reverse Engineering

Abstract: Integrated Circuit (IC) device manufacturing is a challenging task and often results in subtle defects that can render a chip unusable. To detect these defects at multiple stages during the IC production process, test modes are inserted (Design For Testability). On the downside, attackers can use these test modes to break IC device security and extract sensitive information such as the firmware implementation or secret key material. While in high security smart cards the testing circuits are physically removed during production for this reason, in the majority of digital ICs the testing modes remain intact. Often they are undocumented, well-hidden and contain secret test commands. Utilizing search algorithms and/or side channel information, several attacks on secret testing modes have been presented lately. Accordingly, countermeasures that frequently rely on obfuscation techniques have been proposed as more advanced cryptographic methods would require significantly more space on the die and thus cause higher production costs. In this work, we show that limited effort silicon reverse engineering can be effectively used to discover secret testing modes and that proposed obfuscation based countermeasures can be circumvented without altering the analysis technique. We describe our approach in detail at the example of a proprietary cryptographic game authentication chip of a well known gaming console and present an FPGA implementation of the previously secret authentication algorithm.

Design-for-test techniques for a digital electronic circuit

Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.

Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays

Abstract: Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed However, the limited sense-margin poses challenge towards applicability of STTRAM Reference voltage (Vref) biasing and clamp voltage (Vclamp) biasing are possible techniques to balance '0' and '1' sense margins for improved robustness In this paper, we show that Vref and Vclamp biasing are more effective when employed on appropriately sized sense circuit Our investigation also reveals that these two techniques can be used for meeting two different objectives namely, self-calibration and improved testability We show that the proposed sizing and biasing technique can improve both robustness and testability while sacrificing minimum sense margin compared to conventional sense circuit that is designed to provide best sense margin

Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation

Abstract: Traditional design for testability (DFT) is arduous and time-consuming because of the iterative process of testability assessment and design modification. To improve the DFT efficiency, a DFT process based on test point allocation is proposed. In this process, the set of optimal test points will be automatically allocated according to the signal reachability under the constraints of testability criteria. Thus, the iterative DFT process will be completed by computer and the test engineers will be released to concentrate on the system design rather than the repetitive modification process. To perform test point allocation, the dependency matrix of signal to potential test point (SP-matrix) is defined based on multi-signal flow graph. Then, genetic algorithm (GA) is adopted to search for the optimal test point allocation solution based on the SP-matrix. At last, experiment is carried out to evaluate the effectiveness of the algorithm.

On Using Implied Values in EDT-based Test Compression

Abstract: On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded into scan chains. This paper presents a new and comprehensive method to boost performance of sequential test compression and ATPG operations. The approach is primarily aimed at reducing CPU time associated with generating and compressing test patterns. It prevents ATPG from assigning specified values to many inputs in order to cut down a time-consuming backtracking process needed to resolve conflicts leading to compression aborts. The proposed scheme efficiently combines test compression constraints with ATPG. Experimental results obtained for industrial designs illustrate feasibility of the proposed scheme and are reported herein.

A testability allocation method based on Analytic Hierarchy Process and comprehensive weighted

Abstract: Testability allocation is an important process in design for testability, which allocates system-hierarchy testability index hierarchy by hierarchy down to every part of the system. Aiming at the shortage of the existing testability allocation methods, an unconventional allocation method based on Analytic Hierarchy Process (AHP) and comprehensive weighted method is proposed in this paper. On the basis of testability model of system, comprehensive weighted method is used to take use of the influence parameters and weighting coefficients of each unit of the system calculated by Analytic Hierarchy Process to solve allocation values of each unit. Compared with others, this allocation method is simple, requires less calculation and satisfies different demands. This method is applied to a system to verify its validity, the results show that it is able to effectively integrate various influencing factors and reasonably allocate testability index of the system down to units.

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Abstract: Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn't require modifications to the SoC.

Design and code time testability analysis for object oriented systems

Abstract: In last few decades object oriented software design approach is widely chosen by programmers to design any large and complex system. As the complexity of object oriented software increases, design for testability becomes a necessary task for these systems. The performance of testability is also directly affected by software design for testability. Therefore to make the task of testability more effective, smooth, and reliable, we need the concept of design for testability. Design for testability can be applied during the design time as well as code time but both have its own concerns. This paper discusses design for testability analysis to enhance the testability of object oriented systems.

X-Machine Based Testing for Cloud Services

Abstract: In this article we present a tool designed for cloud service testing, able to generate test cases from a formal specification of the service, in form of a deterministic stream X-machine (DSXM) model. The paper summarizes the theoretical foundations of X-machine based testing and illustrates the usage of the developed tool on some examples. It shows in detail how the specification should be written, which are the design for test conditions it should satisfy, in order to assure the generation of high quality test suites for the cloud service.

Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test

Abstract: A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly state the fault coverage figures to be achieved with respect to permanent faults. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation exists between the system company and the device provider. However, purely functional test often shows several limitations due to the limited accessibility that it can gain on some input/output signals. This paper proposes a hybrid approach, in which a suitable hardware module is added outside a microcontroller to increase its functional testability during the operational phase. Experimental results gathered on several industrial cases-of-study are reported, showing the feasibility of the method.

Design-for-testability for multi-cycle broadside tests by holding of state variables

Abstract: This article describes a design-for-testability approach for increasing the transition fault coverage of multi-cycle broadside tests. Earlier methods addressed two-cycle tests. The importance of multi-cycle tests results from the ability to produce more compact test sets than possible with two-cycle tests, from the fact that when multi-cycle tests are applied at-speed, they can detect defects that are not detected by two-cycle tests and from their ability to avoid overtesting of delay faults. The approach described in this article is based on holding the values of selected state variables constant during the functional clock cycles of a multi-cycle broadside test. This allows new tests to be produced, which are different from broadside tests, without relying on nonfunctional toggling of state variables as in earlier methods for two-cycle tests. Experimental results show significant improvements in transition fault coverage using a fixed set of hold configurations for two types of multi-cycle broadside test sets: (1) test sets that are stored and applied from an external tester, and (2) functional broadside test sets that are generated using on-chip hardware.