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Showing papers on "Design for testing published in 2020"


Proceedings ArticleDOI
01 Nov 2020
TL;DR: In this paper, a simple Design for Test (DfT) technique called intentional offset injection is proposed to detect various faults in the op amp, which can provide high fault coverage of 95% with modest area requirements.
Abstract: An operational amplifier (op amp) is a fundamental block used extensively both as a stand-alone device and as a major block embedded in an SoC. To fully characterize an op amp, sophisticated analog and digital testing is required, which is expensive. Fault detection techniques have proved to reduce package cost and test cost by detecting faulty devices early in the test sequence. In this paper, a simple Design for Test (DfT) technique called intentional offset injection is proposed to detect various faults in the op amp. As our proposed method is completely digital, pure digital circuitry can be used, thereby avoiding expensive analog testing. The op amp can be tested with the proposed fault detection method during wafer probe test right after the continuity tests and the faulty devices could be discarded, thereby circumventing time-consuming analog testing. Additionally, our detection scheme can be used for power-on selftest after deployment and for online health monitoring during normal operation. We show that the proposed detection method can provide high fault coverage of 95% with modest area requirements. In this work, we also introduce a detector called digital window comparator which is used to monitor faults in the biasing circuit as well as in the Widlar current reference providing increased fault coverage.

10 citations


Journal ArticleDOI
TL;DR: A next-generation test data compression scheme that builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes.
Abstract: This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein.

9 citations


Proceedings ArticleDOI
01 Feb 2020
TL;DR: The work presents the three different algorithms for implementing controller used in the memory BIST and shows the comparisons of area, power and timing results obtained from RTL compiler for these controller.
Abstract: Design for testability (DFT) help in simplifying the ‘manufacturing tests’ used to detect post fabrication manufacturing defects in an integrated circuits (IC). The embedded memory tests in an integrated circuits utilize Built In Self Test (BIST) strategy. In this paper we have shown BIST technique and several algorithms used in BIST to test embedded memory. Such memory BIST technique comprises of address generator, controller, comparator and memory. The work presents the three different algorithms for implementing controller used in the memory BIST. The modeling of the memory BIST controller is performed using Verilog HDL to verify correctness of these memory controllers which are then synthesized using RTL compiler utilizing TSMC 90 nm and ARM 7 nm technology library. The paper shows the comparisons of area, power and timing results obtained from RTL compiler for these controller.

9 citations


Proceedings ArticleDOI
01 Mar 2020
TL;DR: As with most new technology, more efficient and targeted DfT and BIST will emerge once the failure mechanisms and process dependencies of the devices are better known.
Abstract: Margining Test with either internal or external loopback has become a popular Design for Test (DfT) feature in high-speed SerDes. These SerDes DfT-derived results are becoming more unreliable because SerDes devices are pushing the limits of process variability. In addition, implementing DfT at the high-speed side of a device introduces the age-old problem of performance degradation due to the added circuitry. Given that many of these devices have very little performance margin, it is problematic to cause even a small reduction in performance. This is becoming more apparent with new Ethernet SerDes pushing the 100Gbps data rate. As with most new technology, more efficient and targeted DfT and BIST will emerge once the failure mechanisms and process dependencies of the devices are better known. For now, functional and parametric testing for these SerDes is generally required to make end-users comfortable that these devices are performing to spec and relying on off chip features implementation. Additionally, new DfT techniques and new metrics are being introduced to ensure manufacturing of these products.

7 citations


Proceedings ArticleDOI
02 Nov 2020
TL;DR: This paper proposes RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory and provides a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization.
Abstract: In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool flow is based on commercial 2D tools and smart ways to extend them to conduct M3D design and simulation. We provide a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization. We also conduct IR-drop and thermal analysis on M3D designs to improve the reliability. To enhance the testability of our M3D designs, we develop design-for-test (DFT) methodologies and integrate a low-overhead built-in self-test module into our design for testing inter-layer vias (ILVs) as well as logic circuitries in the individual tiers. Our benchmark design is RISC-V Rocketcore, which is an open source processor. Our experiments show 8.1% of power, 19.6% of wirelength and 55.7% of area savings with M3D designs at iso-performance compared to its 2D counterpart. In addition, our IR-drop and thermal analyses indicate acceptable power and thermal integrity in our M3D design.

4 citations


Proceedings ArticleDOI
17 Jun 2020
TL;DR: This work presents the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI).
Abstract: In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in-memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.

3 citations


Proceedings ArticleDOI
01 Dec 2020
TL;DR: This paper explores ATPG for pattern generation and LBIST (Logic built-in self-test) for testing and finds that the fault coverage achieved is 86.01%.
Abstract: DFT (Design for Testability) is a methodology of testing for manufacturing defects in a chip. DFT consists of scan, ATPG (Automatic test pattern generation) methodologies and the BIST (Built in self-test) methods. This paper explores ATPG for pattern generation and LBIST (Logic built-in self-test) for testing. LBIST is explored and tested using pseudorandom test pattern generation. The fault list created for undetected faults are dumped into ATPG and fault specific test patterns are generated. These patterns detect the random pattern resistant faults (which are undetected by pseudorandom testing patterns). Further, a smart compression algorithm is defined to compress the pattern which can be stored inside the chip for LBIST testing, with no added memory overhead, and the minimum extra hardware (which only comprises of combinational logic). The proposed algorithm has been reviewed and analyzed and it has been found that the fault coverage achieved is 86.01%.

3 citations


Journal ArticleDOI
TL;DR: A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency and sustains an optimal level of performance without incurring any extra DFT (design for testability) cost.
Abstract: A new test data compression scheme for circular scan architecture is proposed in this paper. A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency. In circular scan architecture, test data compression is achieved by updating the conflicting bits between the most recently captured response and test vector to be applied next. The quantity of conflicting bits also manifests the Hamming distance between the most recently captured response and the next test vector. A significant reduction in test data volume and test application time is achieved by reducing Hamming distance. The problem is renovated as a traveling salesman problem (TSP). The test vectors are presumed as cities and Hamming distance between a pair of test vectors is treated as intercity distance and a modified ACO algorithm in combination with mutation operator is applied here to resolve this combinatorial optimization problem. The experimental results confirm the efficacy of this approach. An average improvement of 6.36% in compression ratio and 4.77% in test application time is achieved. The exhibited technique sustains an optimal level of performance without incurring any extra DFT (design for testability) cost.

3 citations


Journal ArticleDOI
TL;DR: A test accessibility architecture based on ternary encoded simultaneous bidirectional signaling (SBS), intended for use in parallel test access mechanism (TAM) in system on chip (SoC)-based designs, is proposed, which reduces the overall test time by up to 53.6% as compared to conventional TAM design methods.
Abstract: In order to meet the increasing demand for more performance with reduced power consumption and chip form-factor, semiconductor manufacturing is moving toward 3-D stacked integrated circuits (SICs). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3-D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or through silicon vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this article, a test accessibility architecture based on ternary encoded simultaneous bidirectional signaling (SBS), intended for use in parallel test access mechanism (TAM) in system on chip (SoC)-based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the overall test time (OTT) by up to 53.6% as compared to conventional TAM design methods.

3 citations


Proceedings ArticleDOI
15 Dec 2020
TL;DR: In this article, the authors proposed an attack on advanced DfT having static masking with XOR-based compressive compression, which is 100% successful whenever at least 6 bits out of 32-bit are observable from the chip under test.
Abstract: Scan-based Design for Testability (DfT) provides high fault coverage, observability, and testability of internal nodes of the chip. It can serve as a medium for the attacker to launch a side-channel attack and thus reveal the secret key embedded in the security-critical-chip. DfT test infrastructures are vulnerable to this type of scan attacks. Advanced DfT techniques such as X-Compactor, X-masking, and X-tolerance were considered to be inherently secure against the basic scan attack. Later on, advanced attacking techniques were proposed to reveal the secret key from advanced DfT infrastructure with a probabilistic success rate of 20.75% in their worst case, i.e., when 64 bits (16 bits from 16 active slices for each AES word) of the round output were observable. In this paper, we propose an attack on advanced DfT having static masking with XOR-based Compression. The attack is 100% successful whenever at least 6 bits out of 32-bit, i.e., 24 bits of the 128-bit round output of AES are observable from the chip under test (CUT). To recover 16 bytes of key, it requires only 4096 plaintexts and takes 1498 milliseconds in the worst-case.

3 citations


Proceedings ArticleDOI
09 Mar 2020
TL;DR: Experimental simulations using a 3D-IC example show that the diagnostic performances of both the direct-type and the middle-type examples are improved by the variability cancellation and reach the practical level.
Abstract: To detect open defects of power TSVs (Through Silicon Vias) in PDNs (Power Distribution Networks) of stacked 3D-ICs, a method was proposed which measures resistances between power micro-bumps connected to PDN and detects defects of TSVs by changes of the resistances It suffers from manufacturing variabilities and must place one micro-bump directly under each TSV (direct-type placement style) to maximize its diagnostic performance, but the performance was not enough for practical applications A variability cancellation method was also devised to improve the diagnostic performance In this paper, a novel middle-type placement style is proposed which places one micro-bump between each pair of TSVs Experimental simulations using a 3D-IC example show that the diagnostic performances of both the direct-type and the middle-type examples are improved by the variability cancellation and reach the practical level The middle-type example outperforms the direct-type example in terms of number of micro-bumps and number of measurements

Proceedings ArticleDOI
12 Jul 2020
TL;DR: A hardware Trojan is designed, which consists of two parts namely Trigger used to activate Trojan and payload, which changes the functionality of the chip normally the payload is an XOR gate, which is effective in finding out the real Trojans.
Abstract: Because of globalization in the semiconductor industry and manufacturing processes, integrated circuits are more exposed to harmful attacks called hardware Trojan. This can be considered as a serious threat to the Integrated circuits. Due to the inclusion of hardware Trojan into the existing circuit, it causes the possible effects like changing the functionality of the circuit and discharges some-secret information to the attacker. In this paper, we designed a hardware Trojan, which consists of two parts namely Trigger used to activate Trojan and payload, which changes the functionality of the chip normally the payload is an XOR gate. 2K×(K-1) Trojans are generated for a one-line trigger merged with one payload line for a circuit with K signal lines. The Trojan is detected by generating test patterns by using standard ATPG Tools which detects conditional stuck-at faults-and allows us to find the Trojan coverage and in addition to that this model is effective in finding out the real Trojans.

Proceedings ArticleDOI
01 May 2020
TL;DR: The simulation results show that the radiation hardened scanning D flip-flop has a reliable radiation resistant ability under the premise of ensuring the correct function.
Abstract: Radiation is one of the main challenges in the design of nanoscale integrated circuits in aerospace equipment Aerospace chips need to be designed based on standard cell libraries that are radiation resistant The design for testability (DFT) based on a specific cell library is a technique to enhance reliability in the chip design process, and the scanning D flip-flop is the indispensable unit required for testability design This paper focuses on the DFT of the radiation resistant chip Aiming at the problem of no scanning D flip-flops in the radiation resistant standard cell library of SMIC 018um, the radiation hardened scan D flip-flops are designed and verified from the circuit and layout levels The simulation results show that the radiation hardened scanning D flip-flop has a reliable radiation resistant ability under the premise of ensuring the correct function Then, by embedding our designed 30 scanning D flip-flops to the SMIC 018um standard cell library, the further evaluation shows that the designed scanning D flip-flops can realize the testability design requirements of the radiation resistant SoC chip

Book ChapterDOI
01 Jan 2020
TL;DR: Work done here involves testing a circuit under test with built in response analyser and vector generator with a monitor to control all the activities and rapidly modifying with the advances in technology as the device shrinks.
Abstract: An efficient design for testability (DFT) has been a major thrust of area for today’s VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

Proceedings ArticleDOI
01 Feb 2020
TL;DR: The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state by analyzing hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM’s states.
Abstract: The aim of the work is to analyze hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM’s states depending on the presence of an unconditional transition, a conditional transition, and the absence of transitions between states of analyzed FSM. The conclusion on additional hardware costs is made on the basis of a comparison of synthesis results of testable HDL-models by means of CAD FPGA. The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state. The best way to organize additional transitions during setting of control FSM in an arbitrary state is the transition for which the total hardware cost estimate for the excitation functions is minimal, taking into account the coding of FSM’s states.

Proceedings ArticleDOI
Salem Abdennadher1, Anne Meixner
07 Jun 2020
TL;DR: An overview of 20 years experiences with defect-based testing of High-Speed I/O (e.g. PCI Express, DDR) justify why defect- based test methods implemented with Design for Test (DfT) circuitry can cover the same faulty behaviors as specification based Test.
Abstract: All device segments rely upon High Speed I/O interfaces to deliver functionality and data rate needs. Industry segments include Mobile computing, Automotive, Internet of Things (IoT), edge computing, AI acceleration, Server computers and Personal computers devices. For over a decade, defect-based test methods have provided robust test coverage which permits test factories to deploy low cost ATE. With advanced process nodes, faster data rates and an increase in I/O types on a product some doubt the capabilities of defect-based test methods. The differing transmission lines in a manufacturing test environment and a system environment lay at the heart of the drawbacks. This paper highlights these differences and provides an overview of 20 years experiences with defect-based testing of High-Speed I/O (e.g. PCI Express, DDR). These experiences justify why defect-based test methods implemented with Design for Test (DfT) circuitry can cover the same faulty behaviors as specification based Test. This paper also discusses potential gaps of commonly used High Speed I/O defect-based test approaches and suggests ways to close them.

Proceedings ArticleDOI
21 Sep 2020
TL;DR: An extensive analysis of Java software packages to evaluate their unit-testability shows that code in software repositories is typically split into portions of very trivial code, nontrivial code that is unit- testable, and code that cannot be unit-tested easily.
Abstract: Most businesses rely on a significant stack of software to perform their daily operations. This software is business-critical as defects in this software have major impacts on revenue and customer satisfaction. The primary means for verification of this software is testing. We conducted a large-scale analysis of Java software packages to evaluate their testability. The results show that code in software repositories is typically split into portions of very trivial code, non-trivial code that is unit-testable, and code that cannot be unit-tested easily. This brings up interesting considerations regarding the use of test coverage metrics and design for testability, which is crucial for testing efficiency and effectiveness, but unfortunately too often an afterthought. Lack of testability is an obstacle to applying tools that perform automated verification and test generation. These tools cannot make up for poor testability of the code and have a hard time in succeeding or are not even applicable without first improving the design of the software system.

Book ChapterDOI
01 Jan 2020
TL;DR: This work is proposing an efficient testing scheme that finds the missing of SWAP gates from nearest neighbor (NN) circuits using only single test pattern and test the circuit by finding a design for testability (DFT) model.
Abstract: Since last couple of years, the field of reversible logic synthesis has progressed significantly. Starting from improved design methodologies to efficient testing algorithms, this field has witnessed several prominent research findings, and still research is going for developing more reliable design techniques. Inspired from existing testing works, here, we are proposing an efficient testing scheme that finds the missing of SWAP gates from nearest neighbor (NN) circuits using only single test pattern. Unlike conventional testing algorithms that highly rely on a set of test vectors, here, we test the circuit by finding a design for testability (DFT) model. This testing scheme is very capable to find not only single missing SWAP gates but also can detect multiple missing of SWAP gates in design using the single test pattern. In order to find the correctness of our approach, we have tested our algorithm over a large spectrum of benchmarks and have compared our obtained results with some peer-reviewed works.

Proceedings ArticleDOI
13 May 2020
TL;DR: To optimize the parameters on the 28nm technology node, like test time, test coverage, power dissipation, the area should be analysed.
Abstract: The complexity and gate counts on chips is growing rapidly on networking application chips, because of s maller lithographic nodes Design for testability (DFT) ensures no manufacturing defect on the VLS I fabricated chips Structured DFT approaches like scan methodology, BIST, MBIST ensure quality Nowadays, DFT itself face critical challenge due to node scaling and it affects the density of the fabricated chip In this paper, to optimize the parameters on the 28nm technology node, like test time, test coverage, power dissipation, the area should be analysed This is the major concern of DFT for ASIC chip designing process

Proceedings ArticleDOI
01 Dec 2020
TL;DR: In this paper, the authors present a test automation work applied on national e-health portal for residents in Norway which has over million monthly visits, and the focus of the work is threefold: delegating automation tasks and increasing reusability of test artifacts; metrics for estimating efficiency when creating test artifacts and designing robust automated test cases.
Abstract: In this paper, we present our test automation work applied on national e-health portal for residents in Norway which has over million monthly visits. The focus of the work is threefold: delegating automation tasks and increasing reusability of test artifacts; metrics for estimating efficiency when creating test artifacts and designing robust automated test cases. Delegating (part of) test automation tasks from technical specialist (e.g. programmer - expensive resource) to non-technical specialist (e.g. domain expert, functional tester) is carried out by transforming low level test artifacts into high level test artifacts. Such transformations not only reduce dependency on specialists with coding skills but also enables involving more stakeholders with domain knowledge into test automation. Furthermore, we propose simple metrics which are useful for estimating efficiency during such transformations. Examples of the new metrics are implementation creation efficiency and test creation efficiency. We describe how we design automated test cases in order to reduce the number of false positives and minimize code duplication in the presence of test data challenge (i.e. using same test data both for manual and automated testing). We have been using our test automation solution for over three years. We successfully applied test automation on 2 out of 6 Scrum teams in Helsenorge. In total there are over 120 automated test cases with over 600 iterations (as of today).

Proceedings ArticleDOI
17 May 2020
TL;DR: A test oriented Click-based controller for the Blade template, which is compatible with commercial EDAs and presents gains of 80% in throughput at the cost of 10% in silicon area and 6% in energy.
Abstract: Blade is a bundled-data asynchronous template to cope with process, voltage, and temperature (PVT) variability. Its timing resilient behavior enables to extend the propagation delay of certain pipeline stages when a timing violation is detected. Despite the recent improvements in the template controller design, the new approaches focus mostly on performance, but the testability of these controllers is not addressed. This paper presents a test oriented Click-based controller for the Blade template, which is compatible with commercial EDAs. The results show that the proposed functional testing approach presents, without the need of scan cells, 100% of fault coverage for stuck-at faults in the controller. In addition to the full testability, the proposed controller also presents gains of 80% in throughput at the cost of 10% in silicon area and 6% in energy.

Proceedings ArticleDOI
01 Nov 2020
TL;DR: In this paper, an at-speed testing approach for bundled data circuits, targeting the micropipeline template, is presented. But the main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths.
Abstract: At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature – by adapting the existing techniques for synchronous or creating new ones from scratch – those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.