Showing papers on "Design for testing published in 2022"

A new online testing technique for reversible circuits

Abstract: Any technology offering zero power dissipation must be reversible. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥ 1. Analysing testability issues in a reversible circuit is an important phenomenon. A new online design-for-testability (DFT) technique for reversible circuits is proposed. The authors’ method yields less overhead in terms of quantum cost as compared to the previous online approaches.

A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing

Abstract: The design for testability (DFT) technology based on scan chains is widely used in industry to increase the testability of circuits. However, it also leads to a potential security problem that attackers can use scan chains as a backdoor to attack a system. Common methods to defend such attacks include disabling the scan chain after manufacturing test or employing some secret keys to encrypt/decrypt scan data or to verify the identities of users. The former would make in-field testing impossible and the latter would require storing keys in memory which might also undergo high risk of memory attacks. In this paper we propose a dynamic-key based secure scan architecture that works together with an intrinsic Physical Unclonable Function (PUF) of chips to defend both scan-based and memory attacks while facilitating both manufacturing and in-field testing. A system equipped with this secure architecture will shift out true circuit responses only when legal test patterns are shifted into the scan chains. Moreover, no test key will be stored in memory, hence no memory attacks are possible. We also leverage the PUF to distinct the legal test patterns for different manufactured chips so as to further protect chips. Analysis results show that our protection scheme can achieve a very high security level without sacrificing system performance, testability and diagnosability.

Test Strategy Optimization Based on Soft Sensing and Ensemble Belief Measurement

Abstract: Resulting from the short production cycle and rapid design technology development, traditional prognostic and health management (PHM) approaches become impractical and fail to match the requirement of systems with structural and functional complexity. Among all PHM designs, testability design and maintainability design face critical difficulties. First, testability design requires much labor and knowledge preparation, and wastes the sensor recording information. Second, maintainability design suffers bad influences by improper testability design. We proposed a test strategy optimization based on soft-sensing and ensemble belief measurements to overcome these problems. Instead of serial PHM design, the proposed method constructs a closed loop between testability and maintenance to generate an adaptive fault diagnostic tree with soft-sensor nodes. The diagnostic tree generated ensures high efficiency and flexibility, taking advantage of extreme learning machine (ELM) and affinity propagation (AP). The experiment results show that our method receives the highest performance with state-of-art methods. Additionally, the proposed method enlarges the diagnostic flexibility and saves much human labor on testability design.

Design Automation and Test Solutions for Monolithic 3D ICs

Abstract: Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and ...

All Digital Low-Cost Built-in Defect Testing Strategy for Operational Amplifiers with High Coverage

Abstract: Backed by standards like ISO26262, achieving near 100% defect coverage is becoming a common reliability requirement in the ever-growing automotive industry. However, achieving high defect coverage in an analog circuit has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. In this work, we present a simple design for testability (DfT) technique that achieves 98% defect coverage for operational amplifiers including Widlar current reference and biasing circuitry. Our robust testing method utilizes purely digital testing circuits and is extremely time-efficient reducing the test cost. The proposed method can be used both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. Also, the digital nature of our method presents a way for defect localization through the recorded bit streams. In this work, we also introduce a simple method to detect defects in the Widlar current reference and the bias current circuit. We validate all our results using extensive transistor-level simulations in UMC65nm technology.

LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations

Abstract: This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on introducing a voltage mismatch in the sense amplifier (SA). This mismatch along with the defects in the cell may bias the SA, leading to an incorrect read output which in turn make the HtD faults detectable. The efficacy of the proposed scheme is evaluated by calculating its detection capability in the presence of resistive defects. Evaluation results obtained for a 20nm STT-MRAM memory design show that the proposed scheme provides HtD fault coverage of 81.8% and 86.5%, on average, for intra-cell and inter-cell defects, respectively, with a negligible area overhead (1.1% for a 2Kbit array). In comparison with conventional March tests, which only detect easy-to-detect (EtD) faults, the proposed DFT technique covers both HtD and EtD faults with a faster approach, namely by using a single read operation. Furthermore, to guarantee that the cells affected by HtD faults trigger an incorrect read output under process variation (PV), a timing strategy based on modifying the control unit of the proposed DFT is suggested. The strategy controls the stress introduced by the DFT unit by altering the timing of DFT control signals. The timing alteration enables the detection of HtD faults in the devices with higher deviations from the nominal one due to PV, avoiding yield loss or test escapes.

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Abstract: Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate not only high-density memory storage, but also energy-efficient computing units. However, the unique challenges related to RRAM fabrication process render the traditional memory testing solutions inefficient and inadequate for high product quality. This paper presents low-cost design-for-testability (DFT) solutions that augment the testing process and improve the fault coverage. A computation-in-memory (CIM) based DFT is realized to expedite the detection and diagnosis of faults by developing logic designs involving multi-row activation. A novel addressing scheme is introduced to facilitate the diagnosis of faults. Reconfigurable logic designs are developed to detect unique RRAM faults that offer features such as programmable reference generations, period, and voltage of operation. DFT implementations are validated on a post-layout extracted platform and testing sequences are introduced by incorporating the proposed DFTs. Results show that more than 2.3× speedup and better coverage are achieved with 6× area reduction when compared with state-of-the-art solutions.

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits

Abstract: The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an [Formula: see text] reversible circuit implemented with [Formula: see text]-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size [Formula: see text] to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

Abstract: Abstract Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme . It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

Abstract: In this research, the normal distribution is assumed to be the product characteristic, and the DITM (Digital Integrated Circuit Test Model) model is used to evaluate the integrated circuits (IC) test yield and test quality. Testing technology lags far behind manufacturing technology due to the different rates of development of the two technologies. As a result, quality control will pose significant challenges in pursuing high-quality near-zero defect products (automotive and biomedical electronics and avionics, etc.). In order to ensure product quality, we propose an effective repeated testing method (three-repetition tests scheme, TRTS), which utilizes the move test guardband (TGB) to improve the test yield and test quality. Based on the data in the International Roadmap for Devices and Systems table in 2021, the DITM model is used to estimate the future trend of semiconductor chip test yield, and the retest method (TRTS) is applied improve the test results. The method of repeated testing can increase the test yield and increase the shipment of semiconductor products. By estimating the test cost and profit, the method of repeated testing can obtain chips with near-zero defects with more corporate profits through increased product shipments.

Study for Requirements Analysis Method of Aviation Equipment Test and Diagnosis

Abstract: As the source of testability design, test and diagnostic requirements analysis plays an important role in the testability development of aviation equipment. In order to solve the problem of lack of effective guidance methods for requirement analysis in domestic aviation equipment testability design, to simultaneously carry out testability design and system function and performance design, and to constrain testability indicators, this paper studies the requirement analysis method of test and diagnostic, and constructs two models—fault diagnostic requirements tradeoff and capability evaluation model and status parameter collection requirements model. It realizes the transformation of testability indicators to deterministic product design requirements and provides a data basis for the realization of equipment health management function. This paper provides guidance for the requirements analysis of aviation equipment test and diagnostic.

Study, implementation and testing of radiation tolerant design for testability solutions for CMS OT FE ASICs

Abstract: Abstract The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.

A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture

Abstract: A PUF based hardware security circuit (PBHSC) is proposed for testable ICs containing design for testability (DFT) circuitry. DFT techniques such as scan chain enhance the controllability and observability of internal nodes of an IC, which leads to vulnerabilities such as IP theft or tampering. The proposed solution restricts unauthorized access to DFT structures by inhibiting enable pin of test circuitry. A PUF based lock and key mechanism enable test circuitry only upon successful authentication of the user. Area and power consumption overheads and the latency of the proposed technique are insignificant as these are independent of the size of the circuit under test (CUT). The proposed technique is compatible with the industry-standard DFT architectures such as scan-chain, BIST, JTAG, etc. The proposed design is implemented on Zynq UltraScale + ZCU102 FPGA and Vivado design suite. Proposed PBHSC utilizes 11 LUTs, 7 registers, 1 clock-buffer, 1 clock-cycle is used to produce output, and consumes 18mW power at 100MHz.

Testability design of spacecraft test equipment based on BIT

Abstract: In this paper, the requirements of power supply and distribution, measurement and control, control and propulsion and other front-end special equipment in the integrated test system of deep space spacecrafts are analyzed, and the testability design method of built-in-test (BIT) of the equipment is studied. It mainly includes the testability design of the key circuit of the board and the device port signal between board and device. Carry out various design of BIT models of analog input / output and digital input / output signals to realize non-destructive or low-loss real-time monitoring of signals. This paper designs a verification environment for BIT function application, and verifies the correctness of BIT design for standard mode and failure mode. It provides a technical method for real-time health diagnosis and failure warning of space equipment in unattended condition.

Research on a system controller fault detection method based on correlation matrix

Abstract: In this paper, based on the correlation matrix, the fault detection method of controller is studied based on the fault diagnosis characteristics of environment control and life support system(ECLSS). Combined with the characteristics of actual system fault diagnosis, the reasons for the existence of the feedback loop are analyzed, the different diagnostic effects caused by voltage and current detection methods are compared, and the detection method of breaking the feedback loop by manual testing is proposed. Through modeling and analysis, complete design ideas and methods are provided for improving testability design of controller products, which can help guide Built-In-Test(BIT) design of controllers.

Test Generation for an Iterative Design Flow with RTL Changes

Abstract: A typical VLSI design flow is iterative, implying that performance, power, area and testability are improved iteratively. With the shift left paradigm, most of the changes made to a design, including to a large extent changes to address testability, occur at the RTL. Test generation is an exception with a gate level netlist being required by ATPG tools. Within an iterative flow, repeated ATPG to reevaluate the testability of a design after its RTL has been changed becomes a bottleneck. To address this bottleneck, the test generation process needs to transform a test set generated for an earlier version of the design into a test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design. The main contribution of the paper is to compute such a mapping after RTL changes and resynthesis produce a new gate level netlist, where signal names may have changed, new signals may have been introduced, and signals that existed earlier may have been removed. Experimental results for industrial circuits with changes made at the RTL show an average of 5-fold reduction in test generation time.

Study on testability design of gas purification subsystem based on correlation matrix

Abstract: Testability modeling and analysis play an increasingly important role in improving the level of testability design of products. Based on the correlation matrix, the testability analysis is carried out with a gas purification subsystem as an example. Aiming at the complex feedback loop caused by the external condition test and the cycle, a method of disconnecting the complex feedback loop is proposed, which improves the testability and fault diagnosis ability of the subsystem, and provides a method guidance for the testability design of other systems.

Next Generation Design For Testability, Debug and Reliability Using Formal Techniques

Abstract: The integration of Design for Testability measures is strictly required when designing complex Integrated Circuits (ICs) to ensure that a good testability prevails in the resulting design. By this, a high-quality manufacturing test can be performed, giving a certain level of confidence that no defects have occurred during the manufacturing process, which potentially tamper with the functional behavior's correctness. However, a high-quality test implies large test data volume and high test application time, yielding high test costs. This effect is even more amplified when testing ICs for safety-critical applications like automotive systems or avionics, enforcing a zero-defect policy. Analogously, specific structures for the Design for Debug and Diagnosis are introduced since similar problems exist when debugging complex systems. Finally, the Design for Reliability is becoming increasingly important in applications like avionics since the introduced system has typically to deal with harsh environmental conditions and, hence, the IC has to exhibit a specific level of robustness to withstand. This paper proposes novel contributions to, in the end, pave the way for the next generation of IC, which can be successfully and reliably integrated even in safety-critical applications. In particular, this paper combines formal techniques, such as the Boolean satisfiability problem and bounded model checking, to propose (I) a novel test access mechanism with embedded compression including an optimization-based retargeting framework, (II) a new hybrid compression architecture to address compression aborts and (II) an effective fault detection mechanism for single transient faults. The proposed measures are evaluated by considering industrial-relevant benchmark candidates, demonstrating their effectiveness and showing that state-of-the-art techniques are outperformed.

Implementation of Checkers for DFT Gaskets using SV/UVM

Abstract: DFT (Design for Testability) is an important additional logic that is inserted in an ASIC across the functional logic to aid post-production testing of the chip and to evaluate the faults in silicon that could have caused due to imperfections in fabrication process. DFT gasket verification is required because DFT is again implemented by Engineers which is prone to human errors. In today's ever-growing complexity of Systems-on-Chip (SoC)s, insufficient or inefficient DFT support due to poor specification, implementation or lax design procedures can suddenly become essential to meet market deadlines and delivering products under budget and tight schedules. The goal of this project is to provide a comprehensive, systematic, and completely automated approach for verification of DFT gaskets. The gaskets have to work predictably being cycle-accurate and in sequence as per expectation. Any deviation from the specification could have serious consequences including chip failure, subsequently causing billions of $ cost. An adoptable, random, predictable, cycle-accurate and robust infrastructure had to be built to verify the DFT gaskets so as to ensure the design is bug free. To be reusable, we have chosen UVM as methodology for environment and SystemVerilog as language for verification. Developing the scenarios in testcases and subsequently checkers for the same was carried out. Here DFT gaskets are On-chip clock controller and SRAM. Working of checkers is to compare the actual data expected data. Exceed application was used for connecting to server, Synopsys VCS was used for simulation and Synopsys Verdi tool for debugging.

Fault diagnosis and fault tolerance

Abstract: Internet: Tremendous advances in integration technology have pushed electronic circuits to become more and more complex. On the other hand, high dependability of electronic systems has become a dominant goal in Industrial Revolution (IR4). Therefore, fault diagnosis and fault tolerance have become more important than ever before, and hence demand has risen for more awareness and research in this area. In addition, complex electronic circuits, which are embedded in safety-critical applications, need assurance of the highest level of reliability. Further, a typical manufacturing test result identifies a large number of circuit defects but even the tested circuits are subjected to failure. Added to it, exhaustive testing of circuits is an impractical approach and attaining complete fault coverage may not be feasible at any cost. Design-for-testability (DFT) and built-in self-test (BIST) techniques are used as alternate test strategies. The use of DFT and BIST methodologies requires additional hardware cost but leaving behind undetected manufacturing defects, wear and tear faults, as well as transient errors. This scenario still poses a threat to the reliable operation of the circuit. Therefore, using the concept of fault-tolerant designs is warranted to concurrently detect, diagnose, and correct a fault defect. This chapter introduces the overall concept of test methodology where fault detection and diagnosis is compactly described briefly in the context of integrated fault management. The later part of this chapter introduces the fault tolerance principles.

A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks

Abstract: Scan chain design can improve the testability of a circuit while it can be used as a side-channel to access the sensitive information inside a cryptographic chip for the crack of cipher key. To secure the scan design while maintaining its testability, this paper proposes a memristor-based secure scan design. A lock and key scheme is introduced. Physical unclonable function (PUF) is used to generate a unique test key for each chip. When an input test key matches the PUF-based key, the scan chain can be used normally for testing. Otherwise, the data in some scan cells are obfuscated by the random bits, which are generated by reading the status of a memristor. As the random bits do not relate to the original test data, an adversary cannot access useful information from scan chain to deduce the cipher key. The experimental results show that the proposed secure scan design can resist all existing attacks while incurring low overhead. Also, the testability of the original design is not affected.

Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity

Abstract: This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier.

An obfuscation scheme of scan chain to protect the cryptographic chips

Abstract: The scan chain, as the most popular structured design for testability (DfT) approach, significantly improves the controllability and observability of the circuit under test (CUT). However, the scan chain can be exploited by the hackers to retrieve the secret information in the cryptographic chip. This work proposes an obfuscation scheme of scan chain with test key. The scan chain is divided into segments by the multiplexers, and the linear feedback shift registers (LFSRs) are constructed by the scan cells in the chain. The selection signals of the multiplexers are controlled by the test key bits, and the two input signals of the multiplexers are the original scan chain data and the feedback data of the corresponding LFSR, respectively. The scan chain works normally if all the key bits are correct. Any wrong key bit leads to the flips on the selection signal of the inserted multiplexer periodically during the test mode, and the scan output is obfuscated. Analysis and simulation results demonstrate that the proposed scheme is resilient against the previous scan-based attacks, while maintaining the advantages of the scan testing,

Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift

Abstract: Transition fault testing is an important component of modern testing for delay defects. Unfortunately, test pattern sets for delay defects tend to be significantly longer than test pattern sets for static defects. In the past, various approaches have been devised to detect static defects during scan shift to reduce test time and increase defect coverage. In this paper, we propose a DFT (Design-For-Test) enhancement to allow delay defects to be detected by stuck-at test patterns during scan shift as well.

Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption

Abstract: The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based scan flip-flop, which is the basic building block of scan chain, is troubled with a set of issues such as mux-induced additional delay and test power among others. The effect of additional delay due to the multiplexer on the functional path (D in path) has started influencing the clock period, particularly at the lower technology nodes for the high-performance design. In this work, we propose two scan flip-flop designs using 10nm FinFET technology to address the problem of mux-induced delay and internal power. The proposed designs have been experimentally validated for performance gain and power reduction and compared to the existing designs.

DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

Abstract: Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires $11N$ test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with $N$ words.

Building Hardware Security Primitives Using Scan-based Design-for-Testability

Abstract: Scan chain is typically used to provide test engineers with complete controllability and observability to the circuit under test to reduce the complexity of VLSI testing. However, it should not be dismissed as just a one-hit-wonder that merely facilitates the test of digital circuits. This study presents a comprehensive review of the recent proposals on how scan chain design can present its versatility as security primitives in different areas of hardware security. More specifically, we elaborate its usage in hardware intellectual property watermarking, fingerprinting, and metering, as well as in the design of physical unclonable functions and counterfeit detection. We analyze the challenges and opportunities in building hardware security primitives using modern scan-based design-for-testability (DfT).

Enhancing At-Speed Testability of Complex Inter-Core IO Interfaces

Abstract: With increased adoption of hierarchical DFT (Design for test) and core based test strategy, there is a great emphasis for effective at-speed testing of inter-core synchronous interfaces. Many design challenges exist which limit efficient usage of functional register reuse based core wrapping to enable it. To address this concern, we propose a novel customized core wrapper cell insertion methodology which allows seamless insertion of functional shared wrapper cells on non-supported sequential endpoints. Experimental results from applying the proposed method on a large hierarchical multi-core design indicate an improvement in shared wrapper cell usage in the range of ~6-8%, which aided in boundary level at-speed transition delay fault coverage increase by ~7.5 to 9% as compared to baseline approach. In cases where usage of shared wrapper cells is entirely infeasible, another alternative method is proposed which uses an overlapped scan configuration scheme to enable at-speed test of delay faults at core boundary. Application of combined test mode in another design showed a gain of 0 to ~92-95% delay fault test coverage improvement at the core boundary.