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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


Papers
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Journal ArticleDOI
TL;DR: The dynamic nature of multisource noise, and the need for online testing to detect such noise errors, is shown, and an online approach based on low-cost double-sampling data checking circuit to test for such noise effects in on-chip buses is proposed.
Abstract: With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM noise effects. In this paper, we show the emergence of multisource noise effects, where multiple DSM noise sources combine to produce functional and timing errors even when each separate noise source itself does not. We show the dynamic nature of multisource noise, and the need for online testing to detect such noise errors. We propose an online approach based on low-cost double-sampling data checking circuit to test for such noise effects in on-chip buses. Based on the proposed circuit, an effective and efficient testing methodology has been developed to facilitate online testing for generic on-chip buses. The applicability of this methodology is demonstrated through embedding the online detection circuit in a bus design. The validated design shows the effectiveness of the proposed testing methodology for multisource noise-induced errors in global interconnects and buses.

27 citations

Proceedings ArticleDOI
Mary P. Kusko1, Bryan J. Robbins1, T.J. Snethen1, Peilin Song1, T.G. Foote1, William V. Huott1 
18 Oct 1998
TL;DR: An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required for the IBM S/390 microprocessor.
Abstract: This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

27 citations

Journal ArticleDOI
TL;DR: A sensor-based BIT scheme that involves designing sensors for each module directly into the device under test (DUD and capturing sensor outputs that are low-frequency DC signals) mitigate any issues related to signal integrity and diversity in the test response capture process.
Abstract: In this article, we propose a sensor-based BIT scheme By using sensors, we mitigate any issues related to signal integrity and diversity in the test response capture process Also, BIT can provide a test framework to estimate specifications during production testing for various modules in a heterogeneous SoC or SiP This scheme involves designing sensors for each module directly into the device under test (DUD and capturing sensor outputs that are low-frequency DC signals A low-frequency mixed-signal tester can capture these sensor responses, analyze them to infer each specific module's performance, and determine the overall pass-fail decision for the DUT The embedded sensors perform the necessary signal conditioning of the DUT output signals, thereby significantly reducing the ATE's response capture and analysis overhead As an example, it's possible to test a digital module for rise time by incorporating an integrator at the output node as a sensor As the output node voltage increases, the integrator's output capacitance charges to a DC value The ATE samples the capacitor's DC voltage at a specific time, and the DC voltage would be proportional to the DUT's rise time In this case, there would be no need to sample the rising waveform, and the ATE's digitizer requirements could be significantly relaxed This example indicates that during production testing, carefully chosen sensors can effectively simplify the overall test procedure

27 citations

Proceedings ArticleDOI
01 Oct 1987
TL;DR: This paper presents the IBM VHDL Design System, a set of Computer Aided Engineering design tools built around the VHSIC Hardware Description Language (VHDL).
Abstract: This paper presents the IBM VHDL Design System. This set of Computer Aided Engineering (CAE) design tools, built around the VHSIC Hardware Description Language (VHDL) and developed for IBM internal use, along with other design automation tools, is used by IBM design engineers to develop computer hardware. The function and operation of each piece of the system is described. IBM usage and some of the problems encountered are also discussed.

27 citations

Proceedings ArticleDOI
19 Sep 2005
TL;DR: Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism, but in this work features are inserted into the user's design which allow the system to be monitored and updated at runtime.
Abstract: Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859