Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
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01 Sep 2003
TL;DR: Experimental results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to the flow, results in a signijicant reduction of scan test data volume and scan test time while maintaining the test quality levels.
Abstract: This paper discusses the adoption of Embedded Deterministic Test (EDT) at InJineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-onChip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive, wireless, and data communication applications are provided. These results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to theflow, results in a signijicant reduction of scan test data volume and scan test time while maintaining the test quality levels.
27 citations
03 Oct 1993
TL;DR: Techniques that help a designer to consider testability features early in the design cycle are discussed, based on which behavioral modifications for testability are suggested to the designer.
Abstract: The paper discusses techniques that help a designer to consider testability features early in the design cycle. The behavioral specification of a design is used to perform high level testability analysis, based on which behavioral modifications for testability are suggested to the designer. Results show that the overhead for incorporating these modifications is minimal. >
27 citations
16 Apr 2007
TL;DR: In this article, a self-test scheme for analog and mixed-signal devices based on die-level process monitoring is proposed, which provides a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits.
Abstract: This paper reports a new built-in self-test scheme for analog and mixed-signal devices based on die-level process monitoring. The objective of this test is not to replace traditional specification-based tests, but to provide a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits. Additionally, the possibility of on-chip process deviation monitoring provides valuable information, which is used to guide the test and to allow the estimation of selected performance figures. The information obtained through guiding and monitoring process variations is re-used and supplement the circuit calibration
27 citations
23 May 2011
TL;DR: A novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing and comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit is proposed.
Abstract: High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65nm industrial technology.
27 citations
13 Sep 2004
TL;DR: Improved design for test techniques are developed to facilitate the debug process and improved design automation techniques to reduce hand-drawn schematics are discussed.
Abstract: A third generation Pentium/sup /spl reg//4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.
27 citations