Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Optimal scan for pipelined testing: an asynchronous foundation

Abstract: This paper addresses the problem of constructing a scan chain such that (1) the area overhead is minimal for latch-based designs, and (2) the number of pipeline scan shifts is minimal. We present an efficient heuristic algorithm to construct near-optimal scan chains. On the theoretical side, we show that part (1) of the problem can be solved in polynomial time, and that part (2) is NP-hard, thus precisely pinpointing the source of complexity and justifying our heuristic approach. Experimental results on three industrial asynchronous IC designs show (1) less than 0.1% extra scan latches for level-sensitive scan design, and (2) scan shift reductions up to 86% over traditional scan schemes.

Concurrent test generation and design for testability

Abstract: Results of test generation for sequential benchmark circuits are presented. Tests were generated by a concurrent test generation program, CONTEST, which uses a simulation-based directed-search method. All the circuits except one circuit were automatically initialized by the test generator. Although 99% coverage was obtained for one circuit, the coverage was lower for the others. One possible reason for this low coverage is that some circuits have a significant fraction of redundant faults in their nonscan sequential version. Partial scan with sequential test generation was applied to four circuits. These designs required 18 to 43% of flip-flops to be scanned, and fault coverage over 99% was obtained in each case. >

A seventh-generation x86 microprocessor

Abstract: An out-of-order, three-way superscalar /spl times/86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three /spl times/86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part.

PowerPC/sup (TM)/ array verification methodology using formal techniques

Abstract: In this paper we discuss the methodology used on PowerPC RISC microprocessors to verify the correctness of embedded array blocks. The functional behavior of these blocks cannot be verified using traditional functional simulators since the search space is too large. Our methodology combines the use of equivalence checking formal methods, simulation using ATPG test vectors, and symbolic trajectory evaluation We discuss how these techniques are applied to verify the operation of an array in during design representation formats. We also discuss how these techniques can be used for checking the consistency of different design representations.

On-line testing of switched-capacitor filters

Abstract: Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent test of analog circuits. >