Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Synthesis of sequential circuits for parallel scan

Abstract: Sequential circuit testing is known to be a difficult problem. The authors present a synthesis for testability (SFT) method to solve this problem. In this approach, some testability features analogous to the traditional scan design are added to the normal logic equations which define the finite state machine (FSM). The augmented FSM is then synthesized with these added features built in. The overhead may thus be reduced as the logic needed to obtain testability is merged with the logic needed for normal functionality. Another advantage of this approach is that the test set length is usually very small; in many cases, the authors obtain a sequential test which is roughly only twice the size of the combinational test set derived for the combinational logic of the sequential circuit. This drastically reduces the test application time without sacrificing the advantages of scan design: high fault coverage and low test generation time. By applying their method to benchmark FSM examples the authors show that the resultant area overhead is also quite low. >

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

Abstract: In this paper, we present a satisfiability (SAT)-based framework for automatically generating test programs that target gate-level stuck-at faults in microprocessors. The microarchitectural description of a processor is first translated into a unified register-transfer level (RTL) circuit description, called assignment decision diagram (ADD), for test analysis. Test generation involves extraction of justification/propagation paths in the unified circuit representation from an embedded module's input-output (I/O) ports to primary I/O ports, abstraction of RTL modules in the justification/propagation paths, and translation of these paths into Boolean clauses in conjunctive normal form (CNF). Additional clauses are added that capture precomputed test vectors/responses at the embedded module's I/O ports. An SAT solver is then invoked to find valid paths that justify the precomputed vectors to primary input ports and propagate the good/faulty responses to primary output ports. Since the ADD is derived directly from a microarchitectural description, the generated test sequences correspond to a test program. If a given SAT instance is not satisfiable, then Boolean implications (also known as the unsatisfiable segment) that are responsible for unsatisfiability are efficiently and accurately identified. We show that adding design for testability (DFT) elements is equivalent to modifying these clauses such that the unsatisfiable segment becomes satisfiable. Test generation at the RTL also imposes a large number of initial conditions that need to be satisfied for successful detection of targeted stuck-at faults. We demonstrate that application of the Boolean constraint propagation (BCP) engine in SAT solvers propagates these conditions leading to significant pruning of the sequential search space which in turn leads to a reduction in test generation time. Experimental results demonstrate an 11.1X speedup in test generation time for test generation at the RTL over a state-of-the-art gate-level sequential generator called MIX, at comparable fault coverages. An unsatisifiability-based DFT approach at the RTL improves this fault coverage to near 100% and incurs very low area overhead (3.1%). Unlike previous approaches that either generate a test program consisting of random instruction sequences or assume the existence of test program templates, the proposed approach constructs test programs in a deterministic fashion from the microarchitectural description of a processor

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Abstract: This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

Automatic insertion of BIST hardware using VHDL

Abstract: A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system. >

Overall consideration of scan design and test generation

Abstract: A complete system which takes the test generation algorithm, the scan cell selection strategy and the structure of the scan chain into account is proposed. It is totally different from the traditional approaches which try to enhance the ability of the individual subject. The goal of this research is to reduce the extra costs caused by the scan design, especially the test application time. Experimental results show that the overall consideration of scan design and test generation can speed up test generation and greatly reduce the amount of test application time. >