Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Electronic design automation [1999 technology analysis and forecast]

Abstract: This article presents an electronic design automation technology analysis and forecast for 1999. The subjects covered include: IC design moving to a higher level of abstraction; IC design reuse; and hardware/software integration.

Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

Abstract: Multi-site testing is a popular and effective way to increase test throughput and reduce test costs The authors pro\pose a test flow with large multi-site testing during wafer test, enabled by a narrow SOC-ATE test interface, and relatively small multi-site testing during final (packaged-IC) test, in which all SOC pins need to be contacted They present a throughput model for multi-site testing, valid for both wafer test and final test, which considers the effects of test time, index time, abort-on-fail and re-test after contact fails Conventional multi-site testing requires sufficient ATE channels to allow testing of multiple SOCs in parallel Instead, a given fixed ATE is assumed, and for a given SOC they design and optimise the on-chip design-for-test infrastructure, in order to maximise the throughput during wafer test The on-chip DfT consists of an E-RPCT wrapper, and, for modularly tested SOCs, module wrappers and TAMs Subsequently, for the designed test infrastructure, they also maximise the test throughput for final test by tuning its multi-site number Finally, they present experimental results for the ITC'02 SOC Test Benchmarks and a complex Philips SOC

Test pattern generation and clock disabling for simultaneous test time and power reduction

Abstract: Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS) '85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method.

Program slicing for hierarchical test generation

Abstract: Sequential Automatic Test Pattern Generation (ATPG) is extremely computation intensive and produces good results only on relatively small designs. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical ATPG which targets one module at a time and abstracts the rest of the design. The technique for obtaining a "constraint slice" for each embedded Module Under Test (MUT) within a design is described in detail. The technique has been incorporated in an automated tool for designs described in Verilog, and results on large benchmark circuits show the significant benefits of the approach.

Conformance test experiments for distributed real-time systems

Abstract: This paper introduces a new technique for testing that a distributed real-time system satisfies a formal timed automata specification. It outlines how to write test specifications in the language of Uppaal timed automata, how to translate those specifications into program code for executing the tests, and describes the results of test experiments on a distributed real-time system with limited hardware and software resources.