Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Enhanced Reduced Pin-Count Test for Full-Scan Design

Abstract: This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction

Abstract: The authors present a novel DFT technique based on multimode Illinois scan architecture (MILS) for low pin count test that simultaneously reduces test data volume and test application time. By using the proposed technique, significant savings in test data volume, and testing time can be obtained without modifying the clock tree of the design and with a very small combinational area overhead. Experimental results for two large industrial circuits show that the test data volume and test application time reduction of the order of 100times can be achieved in all cases with less than 1% area overhead over ILS.

Low-capture-power at-speed testing using partial launch-on-capture test scheme

Abstract: Most previous DFT-based techniques for low-capture-power broadside testing can only reduce test power in one of the two capture cycles, launch cycle and capture cycle. Even if some methods can reduce both of them, they may make some testable faults in standard broadside testing untestable. In this paper, a new test application scheme called partial launch-on-capture (PLOC) is proposed to solve the two problems. It allows only a part of scan flip-flops to be active in the launch cycle and capture cycle. In order to guarantee that all testable faults in the standard broadside testing can be detected in the new test scheme, extra efforts are required to check the overlapping part. In addition, calculation of the overlapping part is different from previous techniques for the stuck-at fault testing because broadside testing requires two consecutive capture cycles. Therefore, a new scan flip-flop partition algorithm is proposed to minimize the overlapping part. Sufficient experimental results are presented to demonstrate the efficiency of the proposed method.

Digital Test Generation and Design for Testability

Abstract: This paper is a tutorial intended primarily for individuals just getting started in digital testing. Basic concepts of testing are described, and the steps in the test development process are discussed. A pragmatic approach to test sequence generation is presented, oriented towards ICs interconnected on a board. Finally, design for testability techniques are described, with an emphasis on solving problems that appeared during the test generation discussion.

Test generation and design-for-testability for flow-based mVLSI microfluidic biochips

Abstract: Advances in flow-based microfluidic biochips offer tremendous potential for biochemical analyses and clinical diag-nostics. However, the adoption of flow-based biochips is hampered by defects that are especially common for chips fabricated using soft lithography techniques. Recently published work on fault detection in flow-based biochips is based on logic-circuit modeling of the microfluidic channels and control valves, followed by classical test generation for digital circuits. However, this approach is not applicable to realistic designs because the circuit model is generated manually and many real defects are mapped to undetectable faults in the logic-circuit model. We present a technique for automated and hierarchical generation of the logic-circuit model from the layout of a flow-based microfluidic chip. Moreover, based on the analysis of untestable faults in the logic-circuit model, we present a design-for-testability (DfT) technique that can achieve 100% fault coverage. Two microfluidic VLSI (mVLSI) chips, each containing over 1500 valves, are used to demonstrate the automated model generation and DfT solutions.