Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
Papers published on a yearly basis
Papers
More filters
••
TL;DR: This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage.
Abstract: One method for the testing of mixed analog/digital integrated circuits involves the digital encoding of analog signals into an aperiodic pulse-density modulated (PDM) serial bit stream and using it to stimulate a device under test (DUT). This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage. Using such design-for-test logic as the 1149.1-1990 JTAG architecture and a typical RAMBIST controller, these analog signal generation techniques can be added to digital integrated circuits (IC's) with minimal additional hardware overhead.
23 citations
••
01 Oct 2006TL;DR: This work introduces a UML-based design approach for complete SoC specification that enables generation of complete synthesizable HDL code and outlines Handel-C code generation for an MP3 decoder design.
Abstract: The continuous advances in manufacturing Integrated Circuits (ICs) enable complete systems on a single chip. However, the design effort for such System-on-Chip (SoC) solutions is significant. The productivity of the design teams currently lags behind the advances in manufacturing and this design productivity gap is still widening. One important reason is the lack of abstraction in traditional Hardware Description Languages (HDLs) like VHDL. The UML provides more abstract concepts for modeling behavior that can also be employed for hardware design. In particular, the new UML Activity semantics fit nicely with the inherent data flow in hardware systems. Therefore, we introduce a UML-based design approach for complete SoC specification. Our approach enables generation of complete synthesizable HDL code. The equivalent hardware can be automatically generated using the existing tools chains. As an example, we outline Handel-C code generation for an MP3 decoder design.
23 citations
••
01 Jan 1993TL;DR: A test methodology that reveals safety-margin problems is presented and allows diagnosis without additional hardware to be demonstrated on a CMOS 10-b, 20-Ms/s ADC for camcorder applications.
Abstract: A test methodology that reveals safety-margin problems is presented. The methodology allows diagnosis without additional hardware. To test the safety margin, the correction logic is inhibited. The coding of the first and second stages actually remains the same, but the first stage output is never decremented before the two stage outputs are combined to form the overall ADC (analog-to-digital converter) output code. This means that over a portion of the second-stage range, the ADC output code will be too high. An example of how a first-stage flash error is interpreted is shown. Here the safety margin is reduced by the shift of the first-stage transition. The technique described here has been demonstrated on a CMOS 10-b, 20-Ms/s ADC for camcorder applications. >
23 citations
••
28 Apr 1996TL;DR: Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.
Abstract: This paper focuses on the implementation of the 'sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.
23 citations
••
TL;DR: The design and implementation of a design-for-test (DfT) architecture is presented, which improves the testability of an asynchronous NoC architecture, and a simple method for generating test patterns for network routers is described.
Abstract: Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
23 citations