Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Cellular automata based deterministic self-test strategies for programmable data paths

Abstract: In this paper, novel and optimized test strategies are presented for the generation of a set of predetermined test vectors on chip to be used as part of a BIST strategy for complex programmable data paths. Starting from a set of faults and a corresponding set of test vectors that cover these faults, the corresponding self-test hardware is determined automatically. For this purpose, a cellular automaton has been made. The CAD tool CAST accomplishes the synthesis of the cellular automaton and the self-test control logic, and evaluates the solution obtained. Dedicated test strategies for 1-pattern tests on the one hand and 1- and 2-pattern tests on the other hand have been developed. These new optimized strategies guarantee a BIST implementation with 100% stuck-at and stuck-open/close fault coverage for all detectable faults. They have been applied to data paths as used in an industrial-size speech processing vocoder design, developed with the silicon compiler CATHEDRAL-II. >

A VHDL implementation of BIST technique in UART design

Abstract: To increase reliability, manufacturers must be able to discover a high percentage of defective chips during their testing procedures. This paper would highlight the attention given by most customers who are expecting the designer to include testability features that will increase their product reliability. This paper focuses on the design of a UART chip with embedded built-in-self-test (BIST) architecture using FPGA technology. The paper starts by describing the behavior of UART circuit using VHISC hardware description language (VHDL). In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements.

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Abstract: Excessive power dissipation caused by large amount of switching activities has been a major issue in scan-based testing. For large designs, the excessive switching activities during launch cycle can cause severe power droop, which cannot be recovered before capture cycle, rendering the at-speed scan testing more susceptible to the power droop. In this paper, we present a methodology to avoid power droop during scan capture without compromising at-speed test coverage. It is based on the use of a low area overhead hardware controller to control the clock gates. The methodology is ATPG (Automatic Test Pattern Generation)-independent, hence pattern generation time is not affected and pattern manipulation is not required. The effectiveness of this technique is demonstrated on several industrial designs.

DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1

Abstract: In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary scan, wherein the proposed DFT allows the verification of the operating frequency range of the CP-PLL while the system is in test mode. This is achieved with a minimal degradation in PLL performance, with lock characteristics remaining unchanged. Simulation results with the layout extracted netlist of the CP-PLL are used to illustrate the working of the technique.

Hierarchical DFT methodology - a case study

Abstract: A hierarchical approach to DFT is presented to address the issues encountered when inserting DFT into large SOC designs. There were challenges in implementing this methodology and the real motivation for implementation of a hierarchical DFT is to align with front-end and physical design process. Implementation of this method includes reduced runtime of tools and reduced pattern size. As a result of additional tester memory available using this technique, more testing was implemented. The case study uses a production design with sandburst, Inc (0.13 /spl mu/, 4 Mgate chip).