Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
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08 Jul 2013
TL;DR: A smart test controller that is able to prevent all known scan attacks is presented, which does not require any additional signals, it is transparent to the designer and it does not requirement any modifications of the test protocol and procedure.
Abstract: Structural testing is one important step in the production of integrated circuits. The most common DIT technique is the insertion of scan-chains, which increases the observability and the controllability of the circuit's internal nodes. Nevertheless, malicious users can use the scan chains to observe confidential data stored in devices implementing cryptographic primitives. Therefore, scan chains inserted in secure ICs can be considered as a source of information leakage. Several countermeasures exist to cope with this type of problem. However, they either introduce high area overheads or they require modifications to the original design or the test protocol. In this paper we present a smart test controller that is able to prevent all known scan attacks. The controller does not require any additional signals, it is transparent to the designer and it does not require any modifications of the test protocol and procedure. Moreover, it introduces a very small area overhead.
22 citations
17 Oct 1993
TL;DR: The Texas Instruments SuperSPARC is a high performance BiCMOS superscalar microprocessor containing 3.1 M transistors aiming towards achieving a highly manufacturable design.
Abstract: The Texas Instruments SuperSPARC is a high performance BiCMOS superscalar microprocessor containing 31 M transistors This paper describes the testability features of this highly integrated processor aiming towards achieving a highly manufacturable design Many of the features described can also be used to test the chip in a system environment The discussion also includes test pattern generation methods and tools used in generating the test vectors Pitfalls and benefits of the techniques used have been summarized in the final section >
22 citations
01 Mar 1999
TL;DR: This work considers four test sequencing problems that frequently arise in test planning and design for testability (DFT) processes and presents various solution approaches to solve them.
Abstract: We consider four test sequencing problems that frequently arise in test planning and design for testability (DFT) processes. Specifically, we consider the following problems: (1) how to determine a test sequence that does not depend on the failure probability distribution; (2) how to determine a test sequence that minimizes expected testing cost while not exceeding a given testing time; (3) how to determine a test sequence that does not utilize more than a given number of tests, while minimizing the average ambiguity group size; and (4) how to determine a test sequence that minimizes the storage cost of tests in the diagnostic strategy. We present various solution approaches to solve the above problems and illustrate the usefulness of the proposed algorithms.
22 citations
TL;DR: A design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits and believes the accuracy of this approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.
Abstract: Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.
22 citations
TL;DR: A description is given of TEA (Test Engineer's Assistant), a CAD environment developed to provide the knowledge base and tools needed by a system designer for incorporating testability features into a design to meet the requirements of fault coverage and ambiguity group size.
Abstract: A description is given of TEA (Test Engineer's Assistant), a CAD (computer-aided design) environment developed to provide the knowledge base and tools needed by a system designer for incorporating testability features into a design. TEA helps the designer meet the requirements of fault coverage and ambiguity group size. Fault coverage is defined as the percentage of faults that can be detected out of the population of all faults of a unit under test with a particular test set. An ambiguity group is defined as the smallest hardware entity in a given level of the system design hierarchy (that is, board, subsystem, and system) to which a fault can be isolated. The fault model considered throughout is the single stuck-at fault model. An example application of TEA is included. >
22 citations