Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

A test evaluation technique for VLSI circuits using register-transfer level fault modeling

Abstract: Stratified fault sampling is used in register transfer level (RTL) fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault-injection algorithms are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed gate-level stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the gate-level coverage within the statistical error bounds. For a very large scale integration system, consisting of several modules, the level of description may differ from module to module. Therefore, the stratified fault sampling technique is used to determine the overall coverage as a weighted sum of RTL module coverages. Several techniques are proposed to determine these weights, known as stratum weights. For a system timing controller application specific integrated circuit, the stratified RTL coverage of verification test-benches is estimated to be within 0.6% of the actual gate-level coverage of the synthesized circuit. This ASIC consists of 40 modules (consisting of 9000 lines of Verilog hardware description language) that are synthesized into 17,126 equivalent logic gates by a commercial synthesis tool. Similar results on two other systems are reported.

Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Abstract: This paper presents the DFT techniques used in Motorola's high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to 1 GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2 % stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.

Design-for-debugging of application specific designs

Abstract: We address the problem of considering debugging requirements during high level synthesis by providing low-cost hardware support and scheduling and assignment methods for ensuring controllability and observability of the user specified variables. Two key conceptually new design ideas that enable efficient debugging are developed: pipelining of debugging variables for improving their scheduling and assignment freedom and use of I/O buffers for improving resource utilization of I/O pins. The provably optimal bounds for the maximum cardinality of the set of controllable and observable variables for a given design specification are derived. A polynomial time complexity synthesis algorithm for achieving the bounds is developed. The minimization of hardware overhead gives rise to a combinatorial optimization problem which is solved using a non-greedy heuristic algorithm. The effectiveness of the proposed Design-for-Debugging approach is demonstrated on several examples.

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Abstract: This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.