Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Channel masking synthesis for efficient on-chip test compression

Abstract: The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow Results are presented to show its effectiveness on some large industrial designs

HSS--A High-Speed Simulator

Abstract: The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation Originally limited to combinational logic, it is being extended to handle sequential logic It may also prove useful as a functional simulator The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a general-purpose computer This compiled code simulates the circuit's response for 16 or 32 test patterns in parallel Faults are injected into the circuit by changing the machine instruction corresponding to the fault location From the range of speeds seen in recent measurements, we take 240 million gates per second as a fair general estimate of the speed of 2-valued simulation running on a 3081/K computer For 3-valued simulation, divide by 29 The paper discusses the merits and drawbacks of the HSS strategy It also sketches the extensions of HSS to model sequential logic and the various applications of HSS These include functional verification, design for testability, good machine signatures, and accurate simulation of transistor-level defects in certain CMOS technologies Finally, there is some discussion of how the simulation requirements of future designs can be met, and of the lessons to be drawn from long-term experimentation with HSS

Application of Saluja-Karpovsky compactors to test responses with many unknowns

Abstract: This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes. The technique, called i-Compact, uses Saluja-Karpovsky Space Compactors, but permits detection and location of errors in the presence of unknown logic (X) values with help from the ATE. The advantages of i-Compact are: 1. Small number of output pins front the compactors for a required error detection capability; 2. Small tester memory for storing expected responses; 3. Flexibility of choosing several different combinations of number of X values and number of bit errors for error detection without altering the hardware compactor; 4. Same hardware capable of identifying the line that produced an error in presence of unknowns; 5. Use of non-proprietary codes found in the literature of 1950s; and 6. Independent of the circuit and the test generator.

Scan Design and Secure Chip

Abstract: Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.

A design-for-test methodology for active analog filters

Abstract: A DFT (design-for-test) methodology to improve the controllability/observability of internal signals in active filters is presented. The normal filter design becomes an 'analog scan' structure in the test mode. The fundamental theory underlying the proposed methodology is presented, followed by an algorithmic description and the results of several case studies. These results are considered from the perspectives of the overhead incurred and the extension of the technique to other analog structures. The DFT algorithm includes not only the modification technique but also a test generation scheme. The algorithm is suitable for silicon compiler and CAD (computer-aided-design) implementation. Experimental results confirm the validity of the methodology. >