Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Design of reconfigurable access wrappers for embedded core based SOC test

Abstract: Testing of embedded core based system-on-chip (SOC) ICs is a well known problem, and the upcoming IEEE P1500 (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SOC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a particular test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers. An automatic procedure for the creation of DfT required for reconfiguration using a graph theoretic representation of core wrappers is also presented. Our method is superior to previously published methods as it admits dynamic reconfiguration of core level scan access structures with little area and delay overhead. Using reconfigurable core wrappers the quality of the SOC test schedule can be improved. Theoretical analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort.

Testing Strategy and Technique for Macro-Based Circuits

Abstract: The increasing complexity of VLSI systems demands structured approaches to reduce both design time and test generation effort. PLA's and scan paths have both been widely reported to be efficient in this sense. This correspondence presents an easily testable structure and its related testing strategies. The circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally, considering the involved macro as an isolated item, and then are expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. Since the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable; several implementation issues are finally investigated.

A Hierarchical Test Scheme for System-On-Chip Designs

Abstract: System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test anti lest access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area anti pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

Reducing scan shifts using folding scan trees

Abstract: In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular design for test technologies for sequential circuits. However, it requires much test application time and test data when applied to circuits with many flip-flops. The new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree. A test pattern including many don't care values is used to configure a fully compatible scan tree in order to reduce the scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of the scan chain and thus reduce the scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts.

Arithmetic pattern generators for built-in self-test

Abstract: Adders, subtracters, ALUs, and multipliers, which are available in many data paths, can be utilized to generate test patterns for built-in self-test. In this paper guidelines for the design of arithmetic pattern generators are developed. Experimental results show that the generated patterns achieve similar fault coverage as pseudo-random sequences and require about the same test length. Hence, instead of adding LFSR-based test registers, arithmetic pattern generators can be used and performance degradation is avoided.