Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Using a manufacturing constraint network to identify cost-critical areas of designs

Abstract: A difficult task in concurrent engineering tasks is to provide appropriate manufacturability feedback to the designer in a timely manner. Many tools provide designers with cost and manufacturability evaluations, but they do not necessarily help the designer to identify what aspects of the design to change in order to improve it from a manufacturing perspective. A computer-assisted concurrent-engineering technology is described which identifies cost-critical tolerances in the design and generates cost-reducing design suggestions. The purpose of the system is to help focus the designer’s attention on the specific aspects of the design that influence manufacturing cost. This can aid the designer in optimizing the manufacturing costs of prismatic, one-off parts created on a CNC machining center. This work uses a program called the Manufacturing Evaluation Agent to produce cost-reducing design suggestions. The Manufacturing Evaluation is made up of two portions: a manufacturing planner and a suggestion generator. The manufacturing planner, P3, takes a design and generates a manufacturing constraint net that represents all manufacturing steps and their sequencing. Each constraint in the network has a label indicating the portions of the design (or manufacturing environment) that gave rise to that constraint. The Suggestion Generator analyzes the manufacturing constraint net to find the cost-critical areas, and uses the labels to find the portions of the design responsible for these cost-critical parts of the manufacturing plan. By pinpointing the cost-critical areas of the design and suggesting alternatives, the Manufacturing Evaluation Agent can help the de-signer to more quickly develop a superior design. This results in more rapid turnaround time, lower cost designs, and fewer engineering change orders once the design is sent to the factory floor.

A physical design tool for built-in self-repairable RAMs

Abstract: In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design

Abstract: Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on three-phase cluster partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented. >

Cooperation of synthesis, retargetable code generation and test generation in the MSS

Abstract: The authors report how the different tools in the MIMOLA hardware design system MSS are used during a typical design process. Typical design processes are partly automatic and partly manual. They include high-level synthesis, manual post-optimization, retargetable code generation, testability evaluation and simulation. It is shown how consistent tools can help to solve a variety of related design tasks. There is no other system with an equivalent set of consistent tools. A key point of this work is to show how current high-level synthesis systems can be extended by retargetable code generators which map algorithms to predefine structures. This extension is necessary in order to support manual design modifications. >

System for and Method of Integrating Test Structures into an Integrated Circuit

Abstract: A system and method (1000) for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure (920) integrated into unused backfill space in an IC design which tests a set of dummy devices (940) that are identical to a selected set of devices contained in the IC. The device test structures (920) are selected from a library (920) according to customer requirements and design requirements (1010). The selected test structures are further prioritized (1030) and assigned to design elements within the design in order of priority (1040). Placement algorithms (1060) use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured (950).