Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

On combining design for testability techniques

Abstract: In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty.

A Decorrelating Design-for-Digital-Testability Scheme for $\Sigma{-}\Delta$ Modulators

Abstract: This paper presents a novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma-Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D3T scheme has the potential to test moderate nonlinearity. The proposed D3T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.

Testing big chips becomes an internal affair

Abstract: With the advent of the so-called system on a chip, or superchip, telling whether a complex integrated circuit is free of manufacturing flaws has become more difficult than ever before. Few believe that any automatic test equipment (ATE) machine of known architecture will be able to test tomorrow's chips as accurately or as thoroughly as yield and reliability considerations demand. It is for this this reason that different approaches to chip testing such as design for testability (DFT), automatic test pattern generation (ATPG), built-in self-test (BIST) an internal scan design are currently being developed.

System-level test synthesis for mixed-signal designs

Abstract: Hierarchical test approaches are a must for large designs due to the computational complexity and tight time-to-market requirements. In hierarchical test synthesis, test design is conducted at a subsystem level where the design complexity is manageable. For analog systems, tests are generally designed at the basic block level. This paper outlines a tool for translating basic block-level tests into system-level tests for large analog systems. Computational effectiveness is achieved by the use of high level models and by a pre-analysis of the system to identify feasible translation paths. A method to compute the fault and yield coverages of the resultant system-level tests is also provided in order to evaluate the translation. Experimental results show that test translation reduces design for testability overhead significantly while satisfying coverage requirements.

Limited access testing: IEEE 1149.4-instrumentation and methods

Abstract: The IEEE 1149.4 standard is now poised for inclusion in a new generation of products. Successful application of this important new standard will depend on the availability of supporting methods and instrumentation. While the standard supplies a common architecture, the test engineer must now supply both method and instrumentation. This paper describes proven instrumentation concepts used to demonstrate IEEE 1149.4 measurements on the MEI test chip. Additionally, the paper discusses how current-stimulus and voltage-measurement techniques can be used to diagnose faulty components in medium sized networks of 75 to 150 components. IEEE 1149.4 tests can be automatically generated rather than hand crafted as in functional testing. Unlike digital resting, the technique does not use fault models. Correct operation is found by examining the deviation from nominal performance, greatly simplifying the test development task.