Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

Abstract: This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

Efficient testbench code synthesis for a hardware emulator system

Abstract: The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to the "design verification crisis ", as it is known among engineers. Today's verification challenges require powerful testbenches and high-performance simulation solutions such as Hardware Simulation Accelerators and Hardware Emulators that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and hardware emulator is becoming a new critical bottleneck. We tackle this problem by partitioning the code running on the software simulator into two sections: the testbench HDL (hardware description language) code that communicates directly with the design under test (DUT) and the rest C-like testbench code. The former section is transformed into synthesizable code while the latter runs in a general purpose CPU. Our experiments demonstrate that the proposed method reduces the communication overhead by a factor of about 5 compared to a conventional hardware emulated simulation

Test features of a core-based co-processor array for video applications

Abstract: This paper describes the Design for Testability and test synthesis of a modular video-processing chip named Co-Processor Array (CPA). A core-based test method has been implemented to enable efficient test pattern generation and verification. The main challenges of this work are the test clock strategy, test control, Design for Testability for the various blocks and busses, and test protocol expansion and simulation at chip-level. The core-based test strategy proved to be well suited for integrated circuits with a modular structure like the CPA. Reduction of time-to-market for redesigns and new versions is achieved with this method by reusing cores including Design for Testability and test pattern generation.

Test economics and design for testability for electronic circuits and systems

Abstract: Providing an examination of the economics of design and test of electronics circuits and systems, this book describes the overall economic effects of design and test decisions facing electronic designers, engineering managers and test engineers at device, board, system and field test stages, and includes issues such as time-to-market and product liability. It also discusses the issues and parameters that can cause variations in test-related costs, and covers cost model creation, and the use/usability of cost models for making design and test decisions.

ABILBO: Analog BuILt-in Block Observer

Abstract: This paper presents a novel multifunctional test structure called Analog BuILt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.