Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

An embedded core DFT scheme to obtain highly compressed test sets

Abstract: This paper presents a novel design-for-test (DFT) technique that allows core vendors to reduce the test complexity of a core they are trying to market. The idea is to design a core so that it can be tested with a very small number of test vectors. The I/O pins of such a "designed for high test compression" (DFHTC) core are identical to the I/O pins of an ordinary core. For the system integrator, testing a DFHTC core is identical to testing an ordinary core. The only difference is that the DFHTC core has a significantly smaller number of test vectors resulting in less test data as well as less test time (fewer scan vectors). This is achieved by carefully combining a parallel "test per clock" BIST scheme inside the core with the normal external testing scheme using a tester. The BIST structure inside the core generates weighted pseudo-random test vectors which detect a large number of faults in the core. Results indicate that such DFHTC cores have a significantly smaller number of test vectors than their ordinary counterparts thereby greatly reducing test time and test storage.

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Abstract: In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip

Abstract: The rapid emergence of three dimensional integration using a ``Through-Silicon-Via'' (TSV) process calls for research activities on testing and design for testability. Compared to the traditional 2D designs, the 3D-SoC poses great challenges in testing, such as three dimensional placement of cores and test resources, severe chip overheating due to the nonuniform distribution of power density in 3D, and 3D test access routing. In this work, we propose an effective and efficient test access routing and resource partitioning scheme to tackle the 3D-SoC test challenges. We develop a simple and scalable 3D-SoC test thermal model for thermal compatibility analysis. We construct a 3-D test access architecture for efficient test access routing, and partition the limited test resources to facilitate a thermal-aware test schedule while minimizing the overall test time. The promising results are demonstrated by extensive simulation on ITC'02 benchmark SoCs.

A self-test system architecture for reconfigurable WSI

Abstract: Progress in wafer scale integration (WSI) has brought the problem of electronic system testing into the semiconductor manufacturing arena. The problem is complicated by the reduced controllability and observability implicit at the full wafer integration level. Structured methods must be employed to generate and apply tests in a hierarchical fashion at the function, chip, and system levels. The author describes a methodology which addresses these problems for both the manufacturing and field test environments. A uniform testing interface is defined for each functional chip (cell), with built-in self-test incorporated whenever possible on all new designs. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different species of functional cells. Details are provided for the function (cell-), chip-, and wafer-level testing standards, as well as for the procedures to be followed at wafer level restructuring and testing. The proposed methods will allow current generation wafer restructuring methods to be applied to the next generation of WSI designs, which will require numerous cell types and increasing on-wafer complexity. >

Clock partitioning for testability

Abstract: An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented. >