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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


Papers
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Journal ArticleDOI
TL;DR: This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of the authors' knowledge.
Abstract: This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Σ-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.

19 citations

Proceedings ArticleDOI
02 Oct 1994
TL;DR: This work considers the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults and proposes a method based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults.
Abstract: A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier (1993). In this work, we give a detailed procedure based on the concepts of the previous work and give experimental results of its application.

19 citations

Proceedings ArticleDOI
03 Oct 2011
TL;DR: Experimental results show that the proposed technique can achieve an improvement of up to 58% in quantum cost and 99% in garbage outputs in average, compared to the previous work.
Abstract: This paper presents a simple technique to convert an ESOP-based reversible circuit into an online testable circuit. The technique does not require redesigning the whole circuit for integrating the testability feature, and no new garbage outputs are produced other than the garbage outputs needed for the ESOP-circuit. With a little extra hardware cost, the resultant circuit can detect online any single-bit errors. Experimental results show that the proposed technique can achieve an improvement of up to 58% in quantum cost and 99% in garbage outputs in average, compared to the previous work.

19 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: The techniques used to test Siemens Embedded DRAM Cores are described and all tests used for standard DRAM's can be applied to the DRAM cores, but only a subset of these are used for any given product.
Abstract: The techniques used to test Siemens Embedded DRAM Cores are described. Test Isolation and Design-For-Test logic is built in to the core interface, while external access and Algorithmic Pattern Generation are handled by a central Test Controller. All tests used for standard DRAM's can be applied to the DRAM cores, but only a subset of these are used for any given product.

19 citations

Proceedings ArticleDOI
18 Nov 2013
TL;DR: The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.
Abstract: Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.

19 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859