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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


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Journal ArticleDOI
TL;DR: This paper shows how the proposed TCC grouping methodology is a general case of the traditional BIST embedding methodology for RTL data paths with both uniform and variable bit width.
Abstract: A new built-in self-test (BIST) methodology for register transfer level (RTL) data paths is presented. The proposed BIST methodology takes advantage of the structural information of the RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in BIST area overhead, performance degradation and test application time. Module output responses from each TCC are checked by comparators leading to substantial reduction in fault-escape probability. Only a single signature analysis register is required to compress the responses of each TCC which leads to high reductions in volume of output data and overall test application time (the sum of test application time and shifting time required to shift out test responses). This paper shows how the proposed TCC grouping methodology is a general case of the traditional BIST embedding methodology for RTL data paths with both uniform and variable bit width. A new BIST hardware synthesis algorithm employs efficient tabu search-based testable design space exploration which combines the accuracy of incremental test scheduling algorithms and the exploration speed of test scheduling algorithms based on fixed test resource allocation. To illustrate TCC grouping methodology efficiency, various benchmark and complex hypothetical data paths have been evaluated and significant improvements over the BIST embedding methodology are achieved.

18 citations

Proceedings ArticleDOI
09 Nov 2003
TL;DR: A layout-aware coverage-driven scan chain ordering methodology is proposed and exact and heuristic algorithms for computing the achievable tradeoffs between path delay fault coverage and both dummy flip-flop and wirelength costs are given.
Abstract: Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wirelength overhead. In this paper we propose a layout-aware coverage-driven scan chain ordering methodology and give exact and heuristic algorithms for computing the achievable tradeoffs between path delay fault coverage and both dummy flip-flop and wirelength costs. Experimental results show that our scan chain ordering methodology yields significant improvements in path delay coverage with a very small increase in wirelength overhead compared to previous layout-driven approaches, and similar coverage with up to 25 times improvement in wirelength compared to previous layout-oblivious coverage-driven approaches.

18 citations

Journal ArticleDOI
TL;DR: A new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit and results in testable circuits that have lower area than the corresponding full scan designs are presented.
Abstract: We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. First, we develop a test machine embedding technique for a given gate-level implementation of a finite state machine. The test machine states are mapped onto the states of the given circuit such that a minimum number of new state variable dependencies are introduced. The composite function is optimized. Experimental results show that our method yields testable machine implementations that have lower area than the corresponding full scan designs. The test generation complexity for our machine implementation is the same as that for a full scan design. To apply the method to large gate-level designs, we partition the circuit into interconnected finite-state machines. Each component state machine can be specified either as its gate-level implementation or as the extracted state diagram. We incorporate test functions into each component finite state machine such that the entire interconnection of the augmented components has the same testability properties as the product machine with a single test function. ISCAS '89 benchmark circuits are partitioned into component finite state machines using a new testability-directed partitioning algorithm. Again, our embedding procedure results in testable circuits that have lower area than the corresponding full scan designs. >

18 citations

Proceedings ArticleDOI
23 Nov 1995
TL;DR: It is shown that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model.
Abstract: Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or testability-targeted synthesis approaches. We show that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model. Every pair of states can easily be distinguished in the modified machine, thus making it easily testable. The augmented logic is also universal, i.e., independent of the state diagram or the circuit structure of the given machine. Analysis of benchmark circuits reveals that its hardware overhead is much less compared to that of full scan design.

18 citations

Proceedings Article
29 Dec 2011
TL;DR: In this article, the authors present a method of test pattern generation using 2-D LFSR structures that generate a pre-computed test vector followed by random patterns, and a high-level test synthesis algorithm for operation scheduling and data path allocation.
Abstract: Summary form only given. This session contains papers from different areas in ASIC design that focus on design for testability issues. The session starts with an invited paper by Christopher A. Ryan, Texas Instruments, presenting an embedded core test strategy and built-in self-test for systems on a chip. With the increasing number of embedded cores on a single chip the problems to make each core testable also increases. The author presents a core JTAG strategy with BIST and gives examples of its application in an industrial automotive microcontroller. The regular pa.per part starts with a presentation on Built-in Self-Test. It presents a method of test pattern generation using 2-D LFSR structures that generate a pre-computed test vector followed by random patterns. Another paper deals with integrated scheduling and allocation of high-level test synthesis. The authors present a high-level test synthesis algorithm for operation scheduling and data path allocation. Contrary to other works the approach integrates scheduling and allocation by performing them simultaneously. The next pape:r presents a CMOS Low-power mixed A/D ASIC. It describes the principle of radiation detection, the circuit architecture, low power issues, and then addresses built-in test analog subcircuits that have been implemented in the ASIC along with a JTAG module. Finally, test results are presented showing that all the specifications are satisfied. The session ends with a paper on current-testable high-frequency CMOS operational amplifiers. Current-based test stimuli allow detection of some faults which are difficult to detect or are unstable when using conventional voltage-based stimuli. With the presented approach test stimuli selection is simpler since faulty behaviors are observable in the whole frequency band. The impact of the test circuitry, on circuit performance

18 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859