Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Yield enhancement through fast statistical scan test analysis for digital logic

Abstract: To enable fast technology ramp up and stable high yield a good understanding and fast detection of yield detractors is required. This paper focuses on fast statistical analysis of failures in the logic circuit part of SOC's, especially during ramp-up of a new product or technology. The failing chips response to the production test program is the key for a statistical search for systematic yield losses. The scan test method allows diagnosing the failing circuit nodes in the logic based on the chips misbehavior. Intelligent processing and analysis of this information enables identification of important yield detractors. A description of the approach and experimental results are provided

Desing and self-test for switched-current building blocks

Abstract: This switched-current memory cell with a built-in self-test option serves as a building block for a range of analog functions. As an example application, the authors present a divide-by-two circuit for reference signal generation in algorithmic A/D converters. They also describe two self-test approaches for these building blocks and evaluate their effectiveness. The self-test functions are easy to apply, require very little overhead, and result in fault coverage up to 95% for shorts and 60% for open circuits. Analysis reveals that 100% testability may not be achievable in a cost-effective way for mixed-signal circuits.

Design-for-Testability of PLA'S Using Statistical Cooling

Abstract: A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect to multiple stuck-at faults and multiple missing/extra crosspoint faults.

An effort-minimized logic BIST implementation method

Abstract: This paper presents LBIST (Logic Built-In Self Test) design practice at Cisco Systems. It focuses on the LBIST design tasks that could affect design schedules and efforts. These are design timing closure and signature mismatch debugging. Our timing closure technique guarantees timing closure for LBIST insertion without any iteration between synthesis and LBIST insertion. In addition, it guarantees that only one iteration between static timing analysis and LBIST insertion is required to close all timing violations. The signature mismatch debugging technique effectively identifies the causes by indicating the pattern, the scan flip-flop and its operation mode, where the mismatch happens. These techniques save design efforts and the product-to-market time. We have integrated this method into an ASIC design flow. The results of using this flow in a large telecommunication design are described.

Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns

Abstract: This paper presents a scan-based DFT technique that uses limited number of enhanced scan cells to reduce volume of delay test patterns and improve delay fault coverage. The proposed method controls a small number of enhanced scan cells by the skewed-load approach and the rest of scan cells by the broadside approach. Inserting enhanced scan cells reduces test data volume and ATPG run time and improves delay fault coverage. Hardware overhead for the proposed method is very low. The scan inputs where enhanced scan cells are inserted are selected by gain functions, which consist of controllability costs and usefulness measures. A regular ATPG can be used to generate transition delay test patterns for the proposed method. Experimental results show that test data volume is reduced by up to 65% and fault coverage is improved by up to about 6%.