Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

On scan path design for stuck-open and delay fault detection

Abstract: A novel scan path design technique is presented, which facilitates the application of two-pattern tests by transition shifting. The scan path is composed based on the test data set as a graph matching problem. For the reduction of the required test application time, a novel reconfigurable scan path architecture is presented, which is synthesized based on the test data set. This reconfigurable scan path concept is applicable not only to two-pattern test sets but also when the test program has been generated for stuck-at faults. >

Synthesis of symmetric functions for path-delay fault testability

Abstract: A new technique of synthesizing symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit will be 100% robustly path-delay fault testable, if the constituent unate functions are synthesized with two-level irredundant circuits. Non-consecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The hardware overhead of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results reveal that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn reduces testing time as compared to those of the best known earlier methods.

The future of test and DFT

Abstract: Advances in design characteristics and design processes are creating significant challenges to design for testability (DFT) and test. Are DFT and test capabilities developing at a pace that will not limit the rapid growth of the very large semiconductor and computing industries that rely on their capabilities? To answer this question, we must understand the alignment between two fundamental sets of trends: growing chip design requirements and the development of EDA capabilities to address these requirements. I outline some of the design requirement trends and the specific issues they introduce, including: fault models; current handling; and test accuracy.

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

Abstract: This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor test structures are reviewed and corresponding models discussed.

Rescheduling transformations for high level synthesis

Abstract: A new approach is presented to high-level synthesis with self-testability. The motivation for this work is the need to fill the void between the fields of high-level synthesis and design for testability. The approach is based on a new allocation algorithm that maps a scheduled data-flow representation of the behavior into a data-path structure that is testable, with no need for test hardware insertion. An important feature of the approach is the rescheduling of transformations to perform design space exploration, under area, delay, and testability constraints. A significant advantage of this method is that the testability design is well integrated into the framework of high-level synthesis at the behavior level. >