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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


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Proceedings ArticleDOI
12 Nov 1998
TL;DR: The design methodology presented in this paper facilitates I ddq testing by controlling power-supply of the individual cores through JTAG boundary scan and allows Iddq testing on one core at a time.
Abstract: System-on-a-chip (SoC) ICs in deep submicron technologies present major challenges in the implementation of Iddq testing. The problems are increased leakage current due to increasing number of gates as well as due to increased sub-threshold leakage of the individual transistors. While methods such as substrate-bias and low temperature are adequate to reduce sub-threshold leakage in deep submicron technologies, almost no solution is available to address the issue of increased leakage due to enormous size of the SoC design. In this paper, we first present a design-for-test concept to address the issue of high leakage due to the large size of SoC design. Secondly, we provide some design rules that are necessary to make SoC design suitable for Iddq testing. The design methodology presented in this paper facilitates Iddq testing by controlling power-supply of the individual cores through JTAG boundary scan and allows Iddq testing on one core at a time. The design does not require any dedicated pin for this control and area overhead is negligible.

17 citations

Proceedings ArticleDOI
18 Nov 1996
TL;DR: The early estimation of testability in the design phase helps designers to identify parts of the specification that are hard to test; then appropriate transformations can be proposed to enhance the testability of the end product.
Abstract: Communication software has become more complex and therefore more difficult to test. In order to handle the complexity of tests for communication protocols, a research topic known as the design for testability (DFT) has emerged. The main objective of DFT is to reduce the cost and the complexity of tests. Testability activity and its analysis necessitate the use of estimation techniques or measures. The early estimation of testability in the design phase helps designers to identify parts of the specification that are hard to test; then appropriate transformations can be proposed to enhance the testability of the end product.

17 citations

Proceedings ArticleDOI
17 Oct 1993
TL;DR: A new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit is presented, which results in testable circuits that have smaller area than the corresponding full scan designs.
Abstract: We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. We use partition theory and a state variable dependency minimization criterion to map the test function states onto the states of the given circuit. The test generation complexity for our implementation is the same as that for a full scan design. To apply the method to large gate-level designs, we partition the circuit into interconnected finite-state machines. We incorporate test functions into each component machine such that the augmented interconnected machine has the same testability properties as the product machine with test function. Several ISCAS 89 benchmark circuits are partitioned into component finite state machines using a testability-directed partitioned into component finite state machines using a testability-directed partitioning algorithm. Our embedding procedure results in testable circuits that have smaller area than the corresponding full scan designs. >

17 citations

Proceedings ArticleDOI
06 Jan 2007
TL;DR: This paper takes up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing by a careful analysis of the interactions between partitions, and introduces additional test modes to increase the coverage of glue logic by making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal.
Abstract: A hierarchical or "divide-and-conquer" scan test methodology enables us to partition a large SoC into several partitions and perform design-for-testability (DFT) functions such as scan insertion, pattern generation, and pattern validation separately on individual partitions. Since the effort for DFT related tasks grows super-linearly with gate count, partitioning reduces the effort for DFT tasks. Further, test application can be divided into k + 1 modes, where k modes correspond to independent testing of the partitions and the (k + 1)th mode corresponds to a "residual" (or daisy) mode where faults that are not covered by the individual modes are considered. In reality, however, the daisy mode can be a killer and wipe out the benefits of divide-and-conquer testing. This is especially true for partitions that do not have test wrappers. In this paper, we take up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing. By a careful analysis of the interactions between partitions, additional test modes are introduced to increase the coverage of glue logic, at the same time making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal. We refer to this version of hierarchical scan testing as "quiet and optimized divide-and-conquer scan". Experimental results reveal that the proposed technique reduces the test time overhead of the conventional daisy mode by about 20times. In addition, the technique drastically reduces the switching activity in the daisy modes and hence reduces the test power

17 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: This paper addresses the practical implementation of a Design-for-Testability (DfT) technique applicable to digitally-corrected pipelined Analog-to-Digital Converters (ADC) and shows that potentially malfunctioning units can be concurrently identified with low extra circuitry.
Abstract: This paper addresses the practical implementation of a Design-for-Testability (DfT) technique applicable to digitally-corrected pipelined Analog-to-Digital Converters (ADC). The objective of this Dft is to improve both the on-and off-line testability of these important mixed-signal ICs. Because of the self-correction capability, such a kind of converters has some inherent insensitivity to the effect of faults which represents a disadvantage for testing and diagnosis. We will show that potentially malfunctioning units can be concurrently identified with low extra circuitry. In addition, this structure-based DfT scheme can also be useful to reduce the time in production-level testing. A CMOS switched-capacitor 10-b ADC is used as demonstrator of the proposed technique.

17 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859