Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Handbook)

Abstract: Introduction. The IC Design Process and EDA. Tools and Methodologies for System-Level Design. System-level specification and modeling languages. SoC Block Based Design and IP Assembly. Performance Evaluation Methods for MPSoC Design. Processor Modeling and Design Tools. Embedded Software Modeling and Design. Using Performance Metrics to Select Microprocessor Cores for IC Designs. Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis. Cycle-Accurate System-Level Modeling and Performance Evaluation. Micro-Architectural Power Estimation and Optimization. Design Planning. Design and Verification Languages. Digital Simulation. Using Transactional Level Models in a SoC Design Flow. Assertion-based verification. Hardware Acceleration and Emulation. Formal Property Verification. Design for Test. Automatic Test Pattern Generation. Analog and Mixed-Signal Test.

Dynamic Function Verification for System on Chip Security Against Hardware-Based Attacks

Abstract: As chip designs become increasingly complex, there is a corresponding increased vulnerability to malicious circuitry that could be inserted in the design process. Such hardware Trojans can be designed to avoid pre-deployment detection, and thus to potentially launch attacks that could impede the function of the system or compromise the integrity of the data it contains. Given the near impossibility of exhaustive detection of malicious hardware during pre-deployment verification, techniques that enable post-deployment hardware integrity verification can play a vital role in system security. In this paper, we propose a system architecture for performing online verification in a manner that does not impede normal system hardware function. The proposed approach provides a comprehensive architectural design method aimed at system on chip (SoC) based hardware systems that performs run-time testing, detects run-time attacks by Trojans, mitigates them, quarantines the detected malicious hardware modules, and regenerates the lost system functions with modest cost.

Automated test development and test time reduction for RF subsystems

Abstract: Increasing percentage of test cost within the overall manufacturing cost for RF sub-systems results in a need for new, low-cost, and efficient test development methods. A methodology for automating test development for RF systems is presented. Test time reduction is achieved by selecting test signal attributes that can target several parameters at once. Due to its high computational efficiency, the tool can be applied multiple times at early design stages; thus enabling parallel test and design flow.

DFT for test optimisations in a complex mixed-signal SOC - case study on TI's TNETD7300 ADSL modem device

Abstract: The design and integration challenges for SOCs include DFT for test integration to meet the test quality and test cost goals. This work describes the DFT implementation on TNETD7300, a single chip ADSL modem SOC with analog and digital sub-systems, IP cores and embedded memories, to address several test optimisation requirements, including scan architecture support for high-end and low-cost testers, concurrent test of digital logic with analog functions, at-speed testing for logic operating in different clock domains and clock frequencies, testing non-homogeneous IP cores together, configurable memory BIST operation, static and dynamic burn-in, and a comprehensive set of SOC test modes to support these operations. These techniques have significantly influenced the silicon test of this device, and have also influenced the design and test methodology adopted in other similar designs in Texas Instruments.

Tests and measurement

Abstract: Fuelled by worldwide semiconductor sales, the test and measurement industry in 1995 enjoyed a year like few others in living memory. This paper presents an overview of test and measurement technologies and highlights: industry searches for the best testability strategy; methods to probe dense integrated circuit boards and wafers; standard approval for a system-level test bus; and how the equipment community is tackling software testing.