Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Identification of design errors through functional testing

Abstract: Verification of the functionality of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task because it is impossible to completely exercise the specification by exhaustively applying all input patterns. We present a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral error model. First, we generate a reduced number of functional test vectors for each process of the specification by using a new analysis metric which we call bit coverage. The error model based on this metric allows the identification of possible design errors represented by redundancies in the VHDL code. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible design errors due to erroneous interconnections. The bit-coverage provides complete statement, condition and branch coverage; and we experimentally show that it allows the identification of possible design errors. Identification and removal of design errors improves the global testability of a design.

II-DFT: a hybrid dft architecture for low-cost high quality structural testing

Abstract: This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to industrial designs demonstrate significant savings in test cost in terms of test data volume and test application time without compromising test quality. Implementation of the HDFT architecture on Intel ASIC and microprocessor designs are described.

Integrated circuit design, fabrication, and test

Abstract: All aspects of chip realization for both digital and analog circuits are covered. Electronics engineers are shown how to choose appropriate technololgy and circuit architecture, and plan the IC design. They'll gain expert information on power consaiderations, the advantages and disadvantages of each IC architecture, and aspects of design for testability.

Synchronizing the IEEE 1149.1 test access port for chip level testability

Abstract: IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.

An efficient compact test generator for I/sub DDQ/ testing

Abstract: We present an algorithm for generating compact test sets for I/sub DDQ/ testing. The faults considered are: (1) the bridging faults (BFs) between gates and (2) the leakage faults (LFs) within a gate. For the LFs within a gate, we propose a fault model called the Input Fault model (IF). The advantages of the IF model include: (1) it is independent of the physical implementation of the logic design, (2) it guarantees the detection of all internal LFs for any implementation, and (3) the total number of faults is relatively small. We utilize the detectability to guide target fault selection during test generation which leads to a compact set of final patterns. We extend the essential fault (ESF) concept and use it for evaluating the detectability of each fault implicitly. The experimental results show that the size of test set generated based on the proposed method is smaller than those obtained by previously proposed procedures.