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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


Papers
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Proceedings ArticleDOI
20 Jun 2004
TL;DR: An implementation of built-in self-test (BIST) design of motion estimation (ME) computing array, which is the main part of MPEG-2 video encoder, is presented.
Abstract: This paper presents an implementation of built-in self-test (BIST) design of motion estimation (ME) computing array, which is the main part of MPEG-2 video encoder. The goal of the design is to offer high reliability for the coding system. Our design is carried out on gate level in both VHDL and Verilog HDL and then synthesized into FPGA. Design verification is also performed using logic simulation and fault simulation.

16 citations

Proceedings ArticleDOI
26 Oct 2004
TL;DR: A simple DFT structure is proposed to enable the on-chip generation of the impulse response signatures from the corresponding step responses of the circuit components, which circumvents the need to apply pseudorandom patterns and perform complex on- chip cross-correlation for IR generation.
Abstract: A technique for testing analog and mixed-signal linear circuit components based on their impulse response (IR) signatures is presented in This work. A simple DFT structure is proposed to enable the on-chip generation of the impulse response signatures from the corresponding step responses of the circuit components. The proposed technique circumvents the need to apply pseudorandom patterns and perform complex on-chip cross-correlation for IR generation. A set of post processing steps based on cross/auto-correlation are proposed to efficiently compare IR signatures. A statistical approach based on linear regression and outlier analysis is used for defect screening. A continuous-time active state variable filter benchmark circuit is used as the device-under-test as a means of validating this technique. The detection sensitivity for shorting and open resistive faults across various defect severity levels is analyzed. The detection results are compared and shown to be superior to a typical specification based test.

16 citations

Proceedings ArticleDOI
18 Nov 2002
TL;DR: In this article, a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design is proposed to minimize the test time and the TAM routing cost while considering test conflicts and power constraints.
Abstract: We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design to minimize the test time and the TAM routing cost while considering test conflicts and power constraints. The main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

16 citations

Proceedings ArticleDOI
01 Nov 1997
TL;DR: The results shows that the MNABST-1 IC device can emulate the capabilities of in-circuit test for most types of components currently tested this way, and preserve the advantages of this well-known technology into the future when direct nodal access will no longer be the rule, but rather the exception.
Abstract: The goals of the studies of the MNABST-1 IC device were as follows: study the technical and economic feasibility of adding P1149.4 structures into mixed-signal devices; elicit design considerations at the silicon level and for silicon design software; study the interoperability of P1149.4 with 1149.1 interconnection test algorithms; study the efficacy of discrete component and network value measurements; establish limits on analog value measurements; and predict the capabilities of P1149.4 in the future. The results shows that we can emulate the capabilities of in-circuit test for most types of components currently tested this way. This will preserve the advantages of this well-known technology into the future when direct nodal access will no longer be the rule, but rather the exception.

16 citations

Proceedings ArticleDOI
Karim Arabi1
19 Apr 2010
TL;DR: Major contributing factors to the growing presence of analog and mixed-signal blocks in SoC designs are discussed and potential solutions to address the issue are examined.
Abstract: With the growing presence of analog and mixed-signal blocks in SoC designs, test and validation cost and quality of mixed-signal circuits is taking the spotlight within the semiconductor industry. This is compounded by the fact that recent innovations in digital test have dramatically reduced the cost of testing digital blocks while analog and mixed-signal blocks are still being tested using brute force methods resulting in a growing contribution of analog test cost to the overall SoC test cost. As a result test cost of mixed-signal blocks in an SoC is becoming an inhibiting factor in commercializing cost effective mixed-signal SoCs. The issue is most pronounced in SoCs with power management and RF components. The normalized cost of test per mm2 of mixed-signal blocks is at least 10 higher than digital blocks. It is therefore imperative for the industry to rapidly advance analog test and characterization to the same level of efficiency as digital in order to effectively manage the test cost and quality of mixed signal SoCs. One of the primary problems is that two of the fundamental building blocks of a test strategy are missing: there is nothing equivalent to automatic test-pattern generation for analog, and that is mainly because there is no practical fault model for analog circuits and DFT and BIST are being used for analog circuits but they are custom efforts for each circuit. The lack of a practical fault model is making it impossible to truncate test effeort while guranteeing test quality before silicon production is fully ramped. In this paper, we will discuss major contributing factors to this trend and examine potential solutions to address the issue. Karim Arabi's bio: Karim Arabi is Sr. Director, Engineering at Qualcomm where he is responsible for leading DFT and EDA across the company. He held key technical management positions at PMC Sierra and Cirrus Logic. Karim was a founder of Opmaxx, Inc., an innovative startup in analog design and test automation, acquired by Credence. Karim's main research interest includes DFT, BIST, low power design, design methodology development and design automation. Karim received his Ph.D. and M.Sc. degrees in Electrical Engineering from Ecole Polytechnique of Montreal and his B.Sc. degree in Elctronics from Tehran Polytechnic.

16 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859