Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Testing for missing-gate faults in reversible circuits

Abstract: Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.

A data path synthesis method for self-testable designs

Abstract: A high level synthesis for testability method is presented whose objective is to generate self-testable RTL designs from data flow behavioral descriptions. The approach is formulated as an allocation problem based on an underlying structural testability model and its connection rules. Two allocation techniques have been developed to solve this problem: one based on an efficient heuristic algorithm that generates cost-effective designs, the other based on an integer linear program formulation that generates optimal designs. The allocation algorithms have been implemented and several benchmark examples are presented.

Radiated Two-Stage Method for LTE MIMO User Equipment Performance Evaluation

Abstract: Two-stage method for long-term-evolution (LTE) multiple-input-multiple-output (MIMO) wireless user equipment (UE) performance evaluation is one of the methods proposed for standard organizations. However, the conducted two-stage method has been challenged for its lack of support for “over-the-air” (OTA) as well as for its negligence of the self-interference in the device under test (DUT) in the throughput test. Self-interference in DUT such as cell phones could significantly reduce receiver sensitivity, thus, if not properly included in the test setup, could affect the test accuracy. In order to solve the problems, a radiated two-stage (RTS) test method for LTE MIMO UE test is presented in this paper. By applying an invert calibration matrix to the input signal of the throughput test, the proposed method performs OTA second-stage test, which eliminates the problems of connecting an RF cable directly to the DUT receiver. The RTS OTA MIMO test method can be executed in a standard single-input-single-output anechoic chamber, reduces overall system cost, and offers high reliability and repeatability. Meanwhile, the measurement provides extensive subcomponent-level performance information and makes it an ideal solution for both research and development (R&D) and certification test.

A reconfigurable shared scan-in architecture

Abstract: In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

On the design of path delay fault testable combinational circuits

Abstract: A theoretical framework for investigating the design for the path-delay-fault testability problem is provided. Necessary and sufficient conditions for the existence of general robust tests in a multioutput, multilevel circuit are given. The conditions for the existence of a more restricted class of robust tests are derived from those for general robust tests. A design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable. A powerful factorization method, that of extended factorization, was exploited for this purpose. >