Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Verification and Analysis of Self-Checking Properties through ATPG

Abstract: Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect and compensate errors online. However, during synthesis and optimization self-checking properties can be destroyed. This paper shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. As a result the properties are either verified or the fault detection profile provided by ATPG can be used to increase the error detection or fault tolerance capabilities of the design. Experimental data are shown for several self-checking arithmetic circuits.

Efficient Analog Defect Simulation

Abstract: Simulation of defects in industrial analog and mixed-signal (A/MS) circuits has long been regarded as impractical: how to simulate the tens of thousands of potential defects for each test and significant process corner of a PLL or SerDes, for example, when simulating each defect could require hours or days of simulation? Would the results for a subset be useful? This paper shows an efficient flow, consistent with the proposed IEEE P2427 Standard for Analog Defect Modeling and Coverage. The flow describes development of realistic models for hard/catastrophic and soft/parametric defects, introduces analog defect collapsing, discusses coverage results for an ITC'17 A/MS benchmark bandgap voltage reference plus LDO voltage regulator, and a programmable PLL, and shows why the results are applicable to large circuits. The results also show that some strategies are more useful than others.

Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II

Abstract: The SFG-tracing methodology addresses the automatic verification of digital synchronous circuit implementations as specified at the algorithmic level as signal- (SFG) or data flow graphs. The SFG-tracing methodology is a multi-level design verification paradigm that aims at bridging the gap between higher level specifications down to lower level implementations up to the transistor switch level. The concepts of the SFG-tracing methodology are illustrated by the automatic verification of a transistor level implementation of a small chip generated from its high level specification by the Cathedral-II silicon compiler. This application, although simple, includes a datapath, register files, a multi-branch micro coded controller, and additional circuitry as necessary for design for testability measures. This application illustrates the SFG-tracing verification methodology as applied to one member of a partitioned SFG behavioral specification. Experimental results on more complex, completely verified designs of 32000 transistors demonstrate the feasibility of the approach. >