Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
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01 Oct 2007
TL;DR: The test methodology presented in this paper reduces design expenses and time to market significantly in comparison with the existing techniques for mixed signal board testing.
Abstract: This paper describes a low cost automatic test methodology for mixed signal boards based on IEEE 1149.4. The uniquely designed test hardware provides the access needed for measurements on a device interface board (DIB) through a device under test (DUT) socket and I/O connectors on the board. A new integrated software environment has been developed to automatically generate functional tests for board verification. This software environment utilizes schematic information, DIB specific constraints, accessibility provided by the test hardware and instrument automation tools to generate a functional test program. The test methodology presented in this paper reduces design expenses and time to market significantly in comparison with the existing techniques for mixed signal board testing.
15 citations
25 May 2008
TL;DR: A testable 2-D motion estimation design at the bit level (TMEbit) based on the C-testability conditions are proposed, and the bit-level cell functions are made bijective in order to meet the testability conditions.
Abstract: In this paper, a testable 2-D motion estimation (TME) design at the bit level (TMEbit) based on the C-testability conditions are proposed. In order to meet the testability conditions, the bit-level cell functions are made bijective. Our C-testability conditions guarantee about 100% fault coverage for single cell fault model with a constant number of test patterns. The number of test patterns is 128. To verify the proposed technique, an experimental chip is implemented with TSMC 0.18 mum technology. According to experimental results, the gate count of the design is about 159 K and the design can operate at the frequency up to 100 MHz. The hardware overhead used to make it C-testable is about 7%.
15 citations
27 Apr 1997
TL;DR: This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs, based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic.
Abstract: Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operation because some errors could not be revealed in the output code under nominal test conditions but could appear when operation conditions change. This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs. The approach is based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic. The effectiveness of the technique has been evaluated by means of fault simulations in a switched-capacitor 10-bit ADC application example.
15 citations
17 Oct 1993
TL;DR: Design for testability efforts on large electronic systems, such as Motorola's IRIDIUM satellites, require a concurrent engineering team approach to be effective and a combination of DFT techniques for the satellite including a satellite-wide multiple chain 1149.1 boundary scan architecture.
Abstract: Design for testability (DFT) efforts on large electronic systems, such as Motorola's IRIDIUM satellites, require a concurrent engineering team approach to be effective. Program DFT strategies and objectives are described that resulted in a combination of DFT techniques for the satellite including a satellite-wide multiple chain 1149.1 boundary scan architecture. >
15 citations
TL;DR: This study examines delay models used in very large scale integration (VLSI) circuit testing based on electrical-level simulation experiments and questions the test quality offered by delay test procedures used so far.
Abstract: In this paper, we examine delay models used in very large scale integration (VLSI) circuit testing. Our study is based on electrical-level simulation experiments. We present a comprehensive analysis of phenomena which significantly affect the actual delays but are not taken into account by the existing models used in testing. Because of these phenomena, for a given path in a circuit, tests commonly considered equivalent may result in different pass/fail decisions. Moreover, contrary to a common assumption, robust tests may fail to detect faults detectable by nonrobust tests. This may happen even in circuits in which all paths are robust testable. Our analysis questions the test quality offered by delay test procedures used so far.
15 citations