Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Design for testability using behavioral models

Abstract: The authors present a systematic approach to analog design-for-testability which uses behavioral models for fault simulation so that objective comparisons can be made between alternative test configurations. This technique of design-for-testability is shown to be especially well suited to an ASIC's (application-specific integrated circuits') environment because the models can be reused and combined to form a library. The fault models should improve with time as more data are collected for a given block. For this reason, a design/experimentation environment has been developed to provide feedback to the system designers. The normal models can also be used to decide what specifications a block will need to function properly in a given system. This is very useful in the design phase for determining how well blocks will fit together, or how much linearity or signal swing a given block will need to achieve a certain high-level system specification. >

Random self-test method applications on PowerPC/sup TM/ microprocessor caches

Abstract: This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that are random as well as self-testing. We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPC/sup TM/ microprocessors is also described. The paper concludes by identifying areas where further work is needed.

A controller testability analysis and enhancement technique

Abstract: This paper presents a testability analysis and improvement technique for the controller of an RT level design. It detects hard-to-reach states by analyzing both the data path and the controller of a design. The controller is modified using register initialization, branch control, and loop termination methods to enhance its state reachability. This technique complements the data path scan method and can be used to avoid scanning registers involved in the critical paths. Experimental results show the improvement of fault coverage with a very low area overhead.

Manufacturing test of SoCs

Abstract: In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.

Pulse shrinkage based pre-bond through silicon vias test in 3D IC

Abstract: Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.