Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Testing the design: the evolution of test simulation

Abstract: In work done in cooperation with Texas Instruments, Analogy, and Teradyne it has been demonstrated that a simulation of a complete test system when combined with design models of an integrated circuit can reduce the cycle time required to get a new product to market. This paper will describe the development of such a system, its inclusion in the design flow for new IC development, and the resulting improvements in new product introduction from the viewpoint of design and test.

Combination of structural and state analysis for partial scan

Abstract: Test generation complexity varies exponentially as the depth of cycles in the S-graph of the circuit. We map the hard-to-reach states obtained from a sequential test generator onto the cycles in the S-graph of the circuit. We then proceed to rank the cycles in terms of the testability gain that would result if the cycle were broken. The primary objective is not to cut all the cycles but to cut those cycles which are preventing the test generator from reaching these hard-to-reach states. To this end, we introduce new measures that combine conventional testability measures such as controllability and observability with the information from hard-to-reach states. We show that this approach overcomes some of the limitations of conventional cycle-cutting. This selective cutting of cycles is shown to yield better results in terms of fault coverage than conventional cycle-cutting.

Design of parity testable combinational circuits

Abstract: The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin are required to complete the design. The test procedure is simple, and the hardware overhead is low. >

High-level variable selection for partial-scan implementation

Abstract: We propose a high level variable selection for partial scan approach to improve the testability of digital systems. The testability of a design is evaluated at the high level based on previously proposed controllability and observability measures. A testability grading technique is utilized to measure the relative testability improvement in a design, as the result of making a subset of the variables fully controllable and observable. The variables that cause the greatest testability improvement are selected and the selection process is performed incrementally until no further testability improvement can be achieved. Then the registers that correspond to the selected variables are placed in the scan chain for partial scan implementation. The experimental results show that the variable selection approach produces partial scan implementations that can achieve high fault coverage, while the logic overheads are fairly low.

Resynthesis of combinational circuits for path count reduction and for path delay fault testability

Abstract: The path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs could be very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points can help reducing the number of such paths in the given design.