Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
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TL;DR: This work proposes to use assist circuits and the inherent memory self-timing mechanism to increase the coverage of small resistive-open defects as well as to specifically screen out those core-cells which are most susceptible to long-term BTI (Bias Temperature Instability) aging.
Abstract: As process technology continues to scale, the test quality, yield and reliability of modern System-on-Chips increasingly depend on their embedded SRAM blocks. Their extreme integration density in conjunction with complex manufacturing process result in subtle lithographic imperfections which demand increasingly effective test solutions to guarantee low DPPM (defective parts per million) rates while keeping test costs low. At the same time, SRAMs are particularly affected by scaling-driven reliability challenges, and addressing them by large aging guard-bands further deteriorates SRAM yield. In this work, we show that built-in circuitry integrated into modern memory architectures can resolve these challenges and eliminate or greatly reduce the need for additional design for testability logic. In particular, we propose to use assist circuits and the inherent memory self-timing mechanism to increase the coverage of small resistive-open defects as well as to specifically screen out those core-cells which are most susceptible to long-term BTI (Bias Temperature Instability) aging. A detailed fault-injection study on an industrial 28nm technology demonstrates that the range of detectable resistances for cell-internal open defects increases by up to 30 percent and potentially unreliable cells prone to BTI aging are screened out. We also suggest a test flow which applies the introduced techniques in an industrial MBIST (memory built-in self-test) environment.
14 citations
07 Sep 1998
TL;DR: A summary of a number of possible DfT approaches that may well help to solve test cost and test quality difficulties for analogue and mixed signal integrated circuits are presented.
Abstract: The cost and complexity of mixed signal and analogue production test programs is lending to considerable interest in Design for testability (DfT) techniques that have the potential to improve testability by reducing implementation cost and improving outgoing quality. These techniques range from rules and guidelines for schematic and physical design to full built-in-self-test (BIST) solutions. This paper presents a summary of a number of possible DfT approaches that may well help to solve test cost and test quality difficulties for analogue and mixed signal integrated circuits.
14 citations
TL;DR: A computer-aided approach to automatic fault isolation in active analog filters which enhances the design-for-test (DFT) methodology proposed by Soma (1990), operationalize and extend the DFT methodology by using CLP(ℜ) to model analog circuits and by a model-based diagnosis approach to implement a diagnostic algorithm.
Abstract: We describe a computer-aided approach to automatic fault isolation in active analog filters which enhances the design-for-test (DFT) methodology proposed by Soma (1990). His primary concern was in increased controllability and observability while the fault isolation procedure was sketched only in general terms. We operationalize and extend the DFT methodology by using CLP(R) to model analog circuits and by a model-based diagnosis approach to implement a diagnostic algorithm. CLP(R) is a logic programming language which combines symbolic and numeric computation. The diagnostic algorithm uses different DFT test modes and results of voltage measurements for different frequencies and computes a set of suspected components. Ranking of suspected components is based on a measure of (normalized) standard deviations from predicted mean values of component parameters. The diagnosis is performed incrementally, in each step reducing the set of potential candidates for the detected fault. Presented case studies show encouraging results in isolation of soft faults of a given low pass biquad filter.
14 citations
07 Apr 1992
TL;DR: The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode, and state-of-the-art simulation techniques used to yield satisfactory experimental results on the ISCAS89 benchmark set.
Abstract: Particular design environments, e.g., those based on partial scan, may prevent design for testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS89 benchmark set. >
14 citations
15 Nov 1994
TL;DR: A novel method to generate test programs for functional verification of microprocessors is presented that combines schemes of random generation and specific sequence generation.
Abstract: A novel method to generate test programs for functional verification of microprocessors is presented. The method combines schemes of random generation and specific sequence generation. Four levels of hierarchical information are used to generate efficient test programs including many complicated sequences. Considerations in the test generation is also discussed. >
14 citations