Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
Papers published on a yearly basis
Papers
More filters
••
TL;DR: In this article, the authors provide a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs.
Abstract: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.
95 citations
••
08 Mar 2010TL;DR: In this paper, the authors focus on the available solutions and still open challenges for testing 3D-SICs and discuss flows for wafer-level and package-level tests, the challenges with respect to test contents and waferlevel probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D SICs.
Abstract: To meet customer's product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing 3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.
94 citations
••
TL;DR: The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations.
Abstract: This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.
94 citations
••
TL;DR: I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification, and the application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated.
Abstract: Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILA's are characterized, as well as CI-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA CI-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design.
94 citations
••
TL;DR: A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented and experimental results indicate that complete fault coverage can be obtained with low hardware overhead.
Abstract: A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to "fix" certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.
93 citations