Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Intelligible test techniques to support error-tolerance

Abstract: We have developed a new digital system mode of operation, referred to as error-tolerance, the purpose of which is to increase effective yield. Error-tolerance is based on the fact that many digital systems exhibit acceptable behavior even though they contain defects and occasionally output errors. A radically new test methodology, called intelligible testing, is required to support error-tolerance. This paper addresses parts of this methodology. There are several fundamental philosophical differences between intelligible testing and classical testing, such as: intelligible testing is application oriented; it partitions die and chips into multiple categories, not just good and bad parts; and it supplies quantitative information about the effects of defects on errors, i.e. it is error based rather than fault based. We describe three types of error attributes, namely error-rate, error-accumulation (retention), and error-significance. We present test techniques for estimating quantitative values for these qualitative attributes. Testing to support error-tolerance involves new ATPG tools, new fault simulators, and new DFT and BIST techniques.

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Abstract: This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.

3D DfT architecture for pre-bond and post-bond testing

Abstract: Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as post-bond stack testing of both partial and complete stacks. The architecture enables on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow flexible optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1500 or IEEE Std 1149.1. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

Methodology for hardware/software co-verification in C/C++ (short paper)

Abstract: In this paper we present our C/C++-based design environment for hardware/software co-verification. Our approach is to use C/C++ to describe both hardware and software throughout the design flow. Our methodology supports the efficient mapping of C/ C++ functional descriptions directly into hardware and software. The advantages of a C/C++-based flow from the verification point of view are presented. The use of C/C++ to model all parts of the system provides great flexibility and enables faster simulation compared to existing methodologies. We show how co-verification can be done efficiently and effectively at the various levels of abstraction, how coverification can be used to drive co-design through performance estimation and give an example of implementation for the 8051 architec-

Limitations and challenges of computer-aided design technology for CMOS VLSI

Abstract: As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation.