Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Optimal configuring of multiple scan chains

Abstract: To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper, the authors consider the problem of optimally constructing the multiple scan chains to minimize the overall test time. Rather than follow the traditional practice of using equal length chains, the authors allow the chains to be of different lengths and show that this cap lead to lower test times. The main idea in this approach is to place those scan elements that are more frequently accessed in shorter scan chains as this tends to reduce the overall test time. Given a design with N scan elements and given that if scan chains need to be used for applying tests, the authors present an algorithm of complexity O(kN/sup 2/) for constructing the specified number of chains such that the overall test application time is minimized. By analyzing a range of different circuit topologies, the authors demonstrate test time reductions as large as 40% over equal length chains. >

Production test challenges for highly integrated mobile phone SOCs — A case study

Abstract: Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded FM radio, and a complete RF transceiver for mobile communication. The paper describes the production test approaches for different groups of embedded circuitry, e.g. digital logic, mixed-signal, etc. Design-for-Test measures are briefly described. A breakdown of relative test times, proportional to production test cost, with respect to different groups of circuitry is presented. Limitations of existing test equipment and future challenges in order to further reduce test cost for complex SOCs are explained based on industrial implementation experience.

A New PLA Design for Universal Testability

Abstract: A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA's. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA's using array folding techniques.

Fully X-tolerant combinational scan compression

Abstract: Traditional scan and, more recently, scan compression are increasingly accepted for reducing test cost and improving quality in ever more complex designs. Combinational scan compression techniques are attractive for their low impact on area, timing and design flow, but are best suited for designs with a limited number of unknowns (Xs). However, recent design performance and cost tradeoffs create a much higher density of Xs than previously expected. We present a combinational scan compression method that preserves the low-impact advantages, while also allowing any number and distribution of Xs with virtually no loss of test quality. Results on industrial designs with a varied density of Xs demonstrate consistent data and test time compressions with negligible impact on all design parameters.

On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

Abstract: The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with the introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations. >