Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Industrial relevance of analog IFA: a fact or a fiction

Abstract: Inductive Fault Analysis (IFA) for analog circuits has received considerable attention in recent years. IFA can be exploited for simplifying various aspects of analog testing. It can also be exploited towards design robustness against process defects, fault grading of a design and examining practicality of analog DfT schemes. In this article, we analyse both aspects of analog IFA with real life examples. Towards the test side, the simulated as well as silicon data demonstrate the strengths of IFA based test methods in test cost reduction and structural test generation. However, some of the escaped devices suggest partial specification testing along with IFA based test is desirable from a quality as well as economic point of view. Towards the design side, the simulation results highlight macros where DfT is needed most and help in determination of effective DfT schemes.

Test and Design-for-Testability in Mixed-Signal Integrated Circuits

Abstract: 0 Introduction.- 1 Mixed-Signal Test.- 2 Analog and Mixed Signal Test Bus: IEEE 1149.4 Test Standard.- 3 Test of A/D Converters.- 4 Phased Locked Loop Test Methodologies.- 5 Behavioral Testing of Mixed-Signal Circuits.- 6 Behavioral Modeling of Multistage ADCs and its Use for Design, Calibration and Test.- 7 DFT and BIST Techniques for Embedded Analog Integrated Filters.- 8 Oscillation-based Test Strategies.

Complexity of sequential ATPG

Abstract: The research reported in this paper was conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation (ATPG) algorithms, which can lead to extremely high test generation times. The retiming transformation is used as a mechanism to create two classes of circuits which present varying degrees of complexity for test generation. It was observed for three different sequential test generators that the increase in complexity of testing is not due to those circuit attributes (namely sequential depth and cycles) which have traditionally been associated with such complexity. Evidence is instead provided that another circuit attribute, termed density of encoding, is a key indicator of the complexity of structural, sequential ATPG. >

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

Abstract: 3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance.

Switching activity generation with automated BIST synthesis for performance testing of interconnects

Abstract: A novel scheme of synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary of the component of a system under test to generate interconnect switching activities that resemble real life interconnect switching profiles is proposed. The goal is to perform at-speed interconnect test while simultaneously capturing the dynamic switching effects such as crosstalk and ground bounce, as accurately as possible during interconnect built-in self-test. A library of nonlinear feedback shift register structures called precharacterized test pattern generators (P-TPGs) is constructed. Components of P-TPGs can be modeled using Markov chain and can be interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. The unique advantage of this scheme is that there is no simulation overhead since P-TPG components are precharacterized by solving Markov equations analytically. An integrated genetic algorithm-based search and optimization technique for finding the best P-TPG component among various possible implementations and matching its activity profiles with those of the interconnections under test has been designed and implemented synthesis for testability allows generation of the worst case interconnect switching activities. Experimental results confirm the validity of our approach.