Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell

Abstract: A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional test techniques. We have shown how to modify the basic concept of OBT to come up with a practical method. Using our approach, designers can use OBT to pave the way for future developments in SoC testing, and it is simple to extend this idea to BIST.

Optimization trade-offs for vector volume and test power

Abstract: In today's large designs, especially large SOC (system-on-a-chip) designs, vector volume for a single core could dominate the memory resources of the target tester and leave little or no room for other vectors. To this end, delivery of an "optimized" or "reduced" vector set, without any loss of coverage, is preferred. One commercial means of delivering an optimized vector set is to compress the vectors during vector generation. Another applicable solutions to understand the overlapping faults among various fault models and remove them from the fault lists for certain pattern types. The main problem with these optimization approaches is that compressed vectors create more switching activities, which could potentially cause average power dissipation, instantaneous and peak power during test to be significantly higher than normal operation. Test power is such a big concern in large SOC designs that the power associated with the "reuse" vectors must be understood. This paper presents a case study of a Motorola Version 3 ColdFire(R) microprocessor core, with a focus on the various vector optimizations and their ramifications on test power.

LSI logic testing — An overview

Abstract: The development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automation. Finally, a brief account of test equipment and test data preparation is given.

Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology

Abstract: This paper investigates parametric and catastrophic fault coverage of the oscillation-test strategy. A set of definitions to evaluate the efficiency of a test technique and to quantify the parametric fault coverage is therefore introduced. The oscillation-test strategy is a low-cost and practical test method which is very efficient for built-in self-testing of mixed-signal integrated circuits. Active analog filters are used as test vehicle and therefore design for testability techniques to convert them to oscillators have been presented. Discrete practical realizations and extensive simulations based on CMOS 1.2 /spl mu/m technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead.

Cellular automata circuits for built-in self test

Abstract: Results are presented for a variation on a built-in self-test (BIST) technique based upon a distributed pseudorandom number generator derived from a one-dimensional cellular automata (CA) array. These cellular automata logic block observation (CALBO) circuits provide an alternative to conventional design for testability circuitry such as built-in logic block observation (BILBO) as a direct consequence of reduced cross-correlation between the bit streams which are used as inputs to the logic unit under test. The issue of generating probabilistically weighted test patterns for use in built-in self test is also addressed. The methodology presented considers the suitability of incorporating structures based on cellular automata, a strategy which, in general, improves test pattern quality. Thus, CA-based structures quality as attractive candidates for use in weighted test pattern generator design. The analysis involved in determining and statistically evaluating these potential models is discussed, and is compared with that for previous as well as statistically independent models. Relevant signature analysis properties for elementary one-dimensional cellular automata are also discussed. It is found that cellular automata with cyclic-group rules provide signature analysis properties comparable to those of the linear feedback shift register. The results presented here are based upon simulation.