scispace - formally typeset
Search or ask a question
Topic

Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


Papers
More filters
Proceedings ArticleDOI
26 Apr 2004
TL;DR: An on-chip scheme for delay fault detection and performance characterization is presented that allows for accurate measurement of delays of speed paths for speed binning and facilitates a systematic and efficient test and debug scheme fordelay faults.
Abstract: Efficient test and debug techniques are indispensable for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. Performance characterization of such chips requires on-chip hardware and efficient debug schemes in order to reduce time to market and ensure shipping of chips with lower defect levels. In this paper we present an on-chip scheme for delay fault detection and performance characterization. The proposed technique allows for accurate measurement of delays of speed paths for speed binning and facilitates a systematic and efficient test and debug scheme for delay faults. The area overhead associated with the proposed technique is very low.

60 citations

Proceedings ArticleDOI
07 Apr 1992
TL;DR: A hybrid scheme is presented that aims to reduce test application time in circuits with full scan by exploiting the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan.
Abstract: Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults. >

60 citations

Patent
James Beausang1
28 Aug 1996
TL;DR: In this paper, a system and method for scan architecting within an integrated circuit design having sub-designs (e.g., modules) is presented, which can be used in an IC design having a hierarchical structure including modules.
Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system environment contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). Individual scan chains are constructed using user defined scan segments and detected inferred segments. Inferred segments are automatically detected if present within IC module designs. When integrated into larger scan chains, the user defined scan segments and the inferred scan segments are not modified during linking. The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define scan configuration information and scan chain specifications (e.g., set scan path commands) to define portions of scan chains. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

60 citations

Proceedings ArticleDOI
01 Nov 1997
TL;DR: A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time.
Abstract: A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.

60 citations

Proceedings ArticleDOI
23 Nov 1995
TL;DR: This paper proposes a programming scheme called block-sliced loading, which makes FPGAs C-testable, and presents two types of programming schemes; sequential loading and random access loading.
Abstract: A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

60 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
85% related
Logic gate
35.7K papers, 488.3K citations
84% related
Integrated circuit
82.7K papers, 1M citations
84% related
Routing (electronic design automation)
41K papers, 566.4K citations
82% related
Benchmark (computing)
19.6K papers, 419.1K citations
80% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859