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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


Papers
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Journal ArticleDOI
TL;DR: The VHSIC hardware description language (or VHDL) provides a standard textual means of description for hardware components at abstraction levels ranging from the logic gate level to the digital system level, enabling design transfer both within and among organizations.
Abstract: The VHSIC hardware description language (or VHDL) provides a standard textual means of description for hardware components at abstraction levels ranging from the logic gate level to the digital system level It provides precise syntax and semantics for these hardware components, enabling design transfer both within and among organizations The language is designed to be efficiently simulated and natural for hardware designers In addition, it allows designers to represent information outside the primary range of language coverage, although the initial toolset does not support simulation at those levels (switch level, for example) Finally, by not restricting designers to a particular hardware technology or design style, the language permits wide industrial usage

57 citations

Proceedings ArticleDOI
10 Jun 2002
TL;DR: It is shown how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be testing with external vectors can be tested with BIST, and the entire SoC can be tests with a low-cost tester.
Abstract: In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC. We present methods for testing, diagnosing, and repairing embedded FPGAs, for which complete testability is achieved without any area overhead or performance degradation. We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with a low-cost tester.

57 citations

Proceedings ArticleDOI
30 Oct 2001
TL;DR: The test and debug features of the Nexperia/sup TM/ PNX8525 chip are presented and the impact of core-based testing is discussed, at both the core-level and the top-level, together with the design-for-debug implementation on this multiple clock domain chip.
Abstract: Decreasing feature sizes and increasing customer demand for more functionality have forced design teams to re-use design blocks and application platforms. As a result, re-use of test, design-for-test and design-for-debug for large system chips is becoming increasingly important and increasingly necessary.. In this paper, the test and debug features of the Nexperia/sup TM/ PNX8525 chip are presented. The PNX8525 chip is a large system chip for the consumer electronics market. The impact of core-based testing is discussed, at both the core-level and the top-level, together with the design-for-debug implementation on this multiple clock domain chip.

57 citations

Proceedings ArticleDOI
03 Oct 2000
TL;DR: The basic goal is to develop a global design for the test methodology and optimization technique for testing a core-based SoC in its entirety and propose an ILP formulation to minimize the hardware cost or the overall access time.
Abstract: We present an optimization method that complies with IEEE P1500 draft standard and deals with modeling and design of the test access mechanism for the SoCs. The basic goal is to develop a global design for the test methodology and optimization technique for testing a core-based SoC in its entirety. We propose an ILP formulation to minimize the hardware cost or the overall access time which also produces the test access schedule.

57 citations

Proceedings ArticleDOI
John A. Nestor1
18 Apr 2002
TL;DR: This work refines the design of a hardware accelerator to support grid-based Maze Routing to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing.
Abstract: This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines their design to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing. An RTL implementation has been developed for this design in VHDL, and initial results show promise for its realization using ASIC, custom, or FPGA technology.

57 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859